Custom IC Design

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Discussion

How to simulate portion of the circuit with pre layout models & remaining circuit with post layout models?

Category: Custom IC Design

By VenkateshTati

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updated over 3 years ago by VenkateshTati

4 replies • 3210 views
Discussion

[Verilog-A/AMS] Using a for loop to instantiate module

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

4 replies • 11540 views
Discussion

[SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and digital output

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 4843 views
Discussion

Can I pass value between runs in Transient Noise simulation?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by FormerMember

6 replies • 11432 views
Discussion

Assert device check w/ pss.hb

Category: Custom IC Design

By Brad RFeng

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updated over 3 years ago by Andrew Beckett

1 replies • 9720 views
Discussion

Simulating a s-par file created with ADS (advanced methodology)

Category: Custom IC Design

By amitG22

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updated over 3 years ago by amitG22

2 replies • 12033 views
Discussion

Calculator error on arithmetic operation on the reading of digital bus

Category: Custom IC Design

By delgsy

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updated over 3 years ago by FormerMember

2 replies • 9619 views
Discussion

LayoutXL creating auto connectivity of custom cell

Category: Custom IC Design

By MattTseng

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updated over 3 years ago by Andrew Beckett

5 replies • 9861 views
Discussion

Layout Cannot Show PDK Instance Graph

Category: Custom IC Design

By ovicovic

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updated over 3 years ago by Andrew Beckett

1 replies • 11160 views
Discussion

About finding the cellname of .oa files

Category: Custom IC Design

By lingtao jiang

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updated over 3 years ago by Andrew Beckett

1 replies • 9000 views
Discussion

Re: command line to select psf directory to allow DC annotation on schematic

Category: Custom IC Design

By slim15

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updated over 3 years ago by Andrew Beckett

1 replies • 9354 views
Discussion

Installscape stops downloading

Category: Custom IC Design

By a2tech

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updated over 3 years ago by Andrew Beckett

1 replies • 8886 views
Discussion

VerilogA SR Latch with digital output

Category: Custom IC Design

By delgsy

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started over 3 years ago

0 replies • 11028 views
Discussion

name of nets inside deepprobe

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

2 replies • 11664 views
Discussion

how to section comment in a DSPF file

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

2 replies • 12350 views

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