Custom IC Design

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Error while running PLL Top simulations with Ultrasim

Category: Custom IC Design

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updated over 18 years ago by archive

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Diva drcAntenna cumulative check

Category: Custom IC Design

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updated over 18 years ago by archive

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Beat frequency in SpectreRF PSS simulation

Category: Custom IC Design

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updated over 18 years ago by archive

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Discussion

neocell

Category: Custom IC Design

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updated over 18 years ago by archive

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Using GTE in PAS 3.1 for generating PDKs?

Category: Custom IC Design

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started over 18 years ago

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Discussion

Impedance setting for ports in Spectre

Category: Custom IC Design

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updated over 18 years ago by archive

4 replies • 17009 views
Discussion

Cadence IC5.141 with NCSU design kit 1.2 or 1.5

Category: Custom IC Design

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updated over 18 years ago by archive

2 replies • 13573 views
Discussion

how does hiCreateInst work for pcells?

Category: Custom IC Design

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updated over 18 years ago by archive

5 replies • 14017 views
Discussion

leiHiCopy ?

Category: Custom IC Design

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updated over 18 years ago by archive

2 replies • 13089 views
Discussion

Error while extracting layout.

Category: Custom IC Design

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updated over 18 years ago by archive

5 replies • 14760 views
Discussion

LVS and "selfmade" mosfet layout in VXL

Category: Custom IC Design

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updated over 18 years ago by archive

2 replies • 6964 views
Discussion

Porting systems (layout) from one technology to another ?

Category: Custom IC Design

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started over 18 years ago

0 replies • 13100 views
Discussion

How to use vcvsp with multiple inputs

Category: Custom IC Design

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updated over 18 years ago by archive

1 replies • 15294 views
Discussion

Defining Spacing Rules inside the technology file

Category: Custom IC Design

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updated over 18 years ago by archive

2 replies • 13512 views
Discussion

How to bind spectre netlist to symbol in schematic

Category: Custom IC Design

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updated over 18 years ago by archive

5 replies • 16868 views

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