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Custom IC Design

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  • Discussion

    AMS simulation Netlist problem

    Category: Custom IC Design

    By milind0z milind0z

    •

    started over 1 year ago

    0 replies • 2897 views
  • Discussion

    automating schematic to post layout simulation flow

    Category: Custom IC Design

    By supriyo1985 supriyo1985

    •

    updated over 1 year ago by supriyo1985

    12 replies • 6763 views
  • Discussion

    How to correctly set the variable simStopNetlistOnPcellFailure?

    Category: Custom IC Design

    By Jonty Jonty

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 3591 views
  • Discussion

    Simulation of differential operational amplier input capacitance

    Category: Custom IC Design

    By Phd SA88 Phd SA88

    •

    started over 1 year ago

    0 replies • 2987 views
  • Discussion

    What is cdsTerm("pin name")?

    Category: Custom IC Design

    By ichiro ichiro

    •

    updated over 1 year ago by ichiro

    2 replies • 1446 views
  • Discussion

    How to set up ADL explorer to run a comparator

    Category: Custom IC Design

    By elshazlio elshazlio

    •

    started over 1 year ago

    0 replies • 3122 views
  • Discussion

    Edit cdf of tsmc devices

    Category: Custom IC Design

    By xared xared

    •

    started over 1 year ago

    0 replies • 3184 views
  • Discussion

    Circular arrays in layout L

    Category: Custom IC Design

    By rb1993 rb1993

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 3370 views
  • Discussion

    Errors due to incorrect pdk file

    Category: Custom IC Design

    By elshazlio elshazlio

    •

    updated over 1 year ago by elshazlio

    2 replies • 3718 views
  • Discussion

    IC618 vs IC231

    Category: Custom IC Design

    By cato cato

    •

    updated over 1 year ago by cato

    2 replies • 5131 views
  • Discussion

    Changing Transient Simulation step size during the simulation

    Category: Custom IC Design

    By AmirMasnadi AmirMasnadi

    •

    updated over 1 year ago by Saloni Chhabra

    1 replies • 3930 views
  • Discussion

    BEOL_STACK choice visible for Pegasus LVS run, but not DRC

    Category: Custom IC Design

    By Saumeek Saumeek

    •

    started over 1 year ago

    0 replies • 3366 views
  • Discussion

    Could anyone explain PSS+PAC simulation result of sampling circuit

    Category: Custom IC Design

    By fvoisin fvoisin

    •

    updated over 1 year ago by fvoisin

    2 replies • 1627 views
  • Discussion

    Pegasus DRC Run fails

    Category: Custom IC Design

    By Saumeek Saumeek

    •

    updated over 1 year ago by RobMan

    2 replies • 4388 views
  • Discussion

    ADE Schemetic simulation will not auto re-netlist Verilog-A Module

    Category: Custom IC Design

    By SimbaG SimbaG

    •

    updated over 1 year ago by Frank Wiedmann

    3 replies • 3835 views
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