Custom IC Design

Latest Posts

Discussion

SystemVerilog generate loop does not compile modules defined inside loop

Category: Custom IC Design

By Nader Fathy

$usertype
•
updated over 3 years ago by SimbaG

2 replies • 11385 views
Discussion

Dc level shifter

Category: Custom IC Design

By Khaleed01

$usertype
•
updated over 3 years ago by FormerMember

3 replies • 10226 views
Discussion

Alter Device Parameter when Device is in Array

Category: Custom IC Design

By Jeff Kauppila

$usertype
•
started over 3 years ago

0 replies • 7818 views
Discussion

How to simulate (equivalent) noise (charge) of CSA?

Category: Custom IC Design

By delgsy

$usertype
•
started over 3 years ago

0 replies • 8051 views
Discussion

Spikes on my signal

Category: Custom IC Design

By Soly

$usertype
•
updated over 3 years ago by FormerMember

5 replies • 11146 views
Discussion

STT MTJ Model

Category: Custom IC Design

By Aswathyn

$usertype
•
started over 3 years ago

0 replies • 8715 views
Discussion

cannot delete extraction cellview

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 8470 views
Discussion

Layour Passing LVS but failing passing PEX extracting calibre. Anyone know why?

Category: Custom IC Design

By FlyingAlbatross

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 11292 views
Discussion

Undo history cleared when saving layout

Category: Custom IC Design

By RicardoGV1

$usertype
•
updated over 3 years ago by Andrew Beckett

4 replies • 11172 views
Discussion

Saving and plotting internal signals within the DSPF extracted view in ADE Explorer

Category: Custom IC Design

By Victor Camacho

$usertype
•
updated over 3 years ago by FormerMember

3 replies • 16229 views
Discussion

what is the meaning of iprobe component in analogLib?

Category: Custom IC Design

By Gordon1002

$usertype
•
updated over 3 years ago by FormerMember

2 replies • 14204 views
Discussion

Plotting from ADE Explorer (netl err)

Category: Custom IC Design

By Sepide

$usertype
•
updated over 3 years ago by Andrew Beckett

5 replies • 17157 views
Discussion

FFT of a signal

Category: Custom IC Design

By Firdos

$usertype
•
updated over 3 years ago by Firdos

5 replies • 18645 views
Discussion

Signal doesn't reach full swing (0 -> VDD) in post-layout spectre tran-simulation

Category: Custom IC Design

By iq79

$usertype
•
updated over 3 years ago by FormerMember

11 replies • 4978 views
Discussion

viaMap in streamout.

Category: Custom IC Design

By kenc184

$usertype
•
updated over 3 years ago by kenc184

2 replies • 9232 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.