Custom IC Design

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Discussion

Error in Simulating Verilog XL+Analog in spectreVerilog

Category: Custom IC Design

By ksnf3000

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updated over 12 years ago by Andrew Beckett

2 replies • 2386 views
Discussion

How to set the model parameter STIMOD in simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Alex Liao

11 replies • 22029 views
Discussion

ADE/ViVA Toggle Trace Visibility Bindkey

Category: Custom IC Design

By mconte

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updated over 12 years ago by mconte

2 replies • 1600 views
Discussion

how to list all devices and their operating region in a file

Category: Custom IC Design

By kxlux

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updated over 12 years ago by Andrew Beckett

1 replies • 15171 views
Discussion

Error in verilogA

Category: Custom IC Design

By sreeni

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updated over 12 years ago by sreeni

4 replies • 16835 views
Discussion

Cadence ADEXL: how to merge troubleshot point with rest of montecarlo data

Category: Custom IC Design

By spectrallypure

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updated over 12 years ago by Frank Wiedmann

12 replies • 20916 views
Discussion

skill to plot waveform contained in a file into w-viewer (could be VIVA)

Category: Custom IC Design

By azde

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updated over 12 years ago by Andrew Beckett

3 replies • 14755 views
Discussion

Is there a way to print model parameter using Hspice-D version2012.03 after running a simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Andrew Beckett

9 replies • 20836 views
Discussion

STB analysis stops running ... with no error in output.log

Category: Custom IC Design

By Praveen K

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updated over 12 years ago by Praveen K

2 replies • 15530 views
Discussion

Ghost of Dragged object

Category: Custom IC Design

By Anonymous

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updated over 12 years ago by Anonymous

2 replies • 14030 views
Discussion

How to search for vias with rows or columsn property in layout XL

Category: Custom IC Design

By pham777

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updated over 12 years ago by pham777

6 replies • 16023 views
Discussion

operating points implementation (verilogA and CDF)

Category: Custom IC Design

By Fabb

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updated over 12 years ago by Andrew Beckett

3 replies • 14384 views
Discussion

importing EDIF file (library install)

Category: Custom IC Design

By oldnick

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updated over 12 years ago by oldnick

2 replies • 17813 views
Discussion

verilogin problem: modules are imported twice

Category: Custom IC Design

By Howel

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updated over 12 years ago by Howel

2 replies • 14837 views
Discussion

Virtuoso Strmout of selected cells

Category: Custom IC Design

By Stevemc12

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updated over 12 years ago by Andrew Beckett

3 replies • 16127 views

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