• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
CDNS - double leaderboard script

Custom IC Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    Error while netlisting in UltrasimVerilog

    Category: Custom IC Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 12617 views
  • Discussion

    SDL flow crash in 6.1?

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13284 views
  • Discussion

    Error while running PLL Top simulations with Ultrasim

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13314 views
  • Discussion

    Diva drcAntenna cumulative check

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13231 views
  • Discussion

    Beat frequency in SpectreRF PSS simulation

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 20947 views
  • Discussion

    neocell

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13458 views
  • Discussion

    Using GTE in PAS 3.1 for generating PDKs?

    Category: Custom IC Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 13966 views
  • Discussion

    Impedance setting for ports in Spectre

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    4 replies • 17020 views
  • Discussion

    Cadence IC5.141 with NCSU design kit 1.2 or 1.5

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13581 views
  • Discussion

    how does hiCreateInst work for pcells?

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    5 replies • 14029 views
  • Discussion

    leiHiCopy ?

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13098 views
  • Discussion

    Error while extracting layout.

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    5 replies • 14768 views
  • Discussion

    LVS and "selfmade" mosfet layout in VXL

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 6965 views
  • Discussion

    Porting systems (layout) from one technology to another ?

    Category: Custom IC Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 13107 views
  • Discussion

    How to use vcvsp with multiple inputs

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 15302 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information