Custom IC Design

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Category: Custom IC Design

By RicardoGV1
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updated over 1 year ago by RicardoGV1

2 replies • 4342 views
Discussion

Pass-gate pmos during vdd rise - forward bias diode (b-d/s)

Category: Custom IC Design

By IKIF
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started over 1 year ago

0 replies • 448 views
Discussion

How to use calculator functions like value(), cross(), or abCrossTwoWaves() for array-like signals?

Category: Custom IC Design

By DomiHammerfall
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started over 1 year ago

0 replies • 5122 views
Discussion

spectre: save parameter before alter statement and revert for later analyses

Category: Custom IC Design

By Zol
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started over 1 year ago

0 replies • 4066 views
Discussion

Temperature in ocean script

Category: Custom IC Design

By Martinsh
•
updated over 1 year ago by Martinsh

2 replies • 4437 views
Discussion

Cadence License Error (DB-320001)

Category: Custom IC Design

By Leo 93
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updated over 1 year ago by Andrew Beckett

4 replies • 5827 views
Discussion

ADEXL 1921 failed to start problem with virtuoso IC6.18

Category: Custom IC Design

By hesaliveJim
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updated over 1 year ago by Andrew Beckett

3 replies • 5397 views
Discussion

With large Verilog-A, SPECTRE fails to run

Category: Custom IC Design

By mfkasim1
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started over 1 year ago

0 replies • 4040 views
Discussion

Very slow ADEXL datasheet generation

Category: Custom IC Design

By markris
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updated over 1 year ago by markris

7 replies • 5715 views
Discussion

Liberate license issue

Category: Custom IC Design

By VardhanPES
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updated over 1 year ago by Guangjun Cao

1 replies • 7020 views
Discussion

Verilog-A syntax error with user-defined function and if-else statement

Category: Custom IC Design

By gjeong35
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updated over 1 year ago by Andrew Beckett

1 replies • 6009 views
Discussion

How to short two nets with different names in layout.

Category: Custom IC Design

By mars32
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updated over 1 year ago by Andrew Beckett

1 replies • 5216 views
Discussion

HB simulation with temperature update after each run

Category: Custom IC Design

By Martinsh
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updated over 1 year ago by Martinsh

2 replies • 4532 views
Discussion

How to generate netlist without virtuoso

Category: Custom IC Design

By yuanshangu
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updated over 1 year ago by Andrew Beckett

2 replies • 6605 views
Discussion

How to process a digital signal in caculator

Category: Custom IC Design

By wangyunxin
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started over 1 year ago

0 replies • 4265 views

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