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Custom IC Design

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  • Discussion

    ASCII waveform file format for Virtuoso Visualization and Analysis XL?

    Category: Custom IC Design

    By Andy Stewart

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    updated over 12 years ago by Andrew Beckett

    6 replies • 19144 views
  • Discussion

    Connectivity->Update->Layout Parameters problem

    Category: Custom IC Design

    By pham777

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    updated over 12 years ago by pham777

    9 replies • 5606 views
  • Discussion

    OCEAN write generic procedure to plot waveforms

    Category: Custom IC Design

    By The Setlaz

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    updated over 12 years ago by The Setlaz

    6 replies • 15354 views
  • Discussion

    Problem simulating Spice Netlist with Spectre

    Category: Custom IC Design

    By Oriba

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    •

    updated over 12 years ago by Andrew Beckett

    7 replies • 20293 views
  • Discussion

    Relative include path for a vpwlf source

    Category: Custom IC Design

    By TonySal

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    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 15080 views
  • Discussion

    ADE XL annotation affects schematic hierarchy

    Category: Custom IC Design

    By Rowlf

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    •

    updated over 12 years ago by Rowlf

    2 replies • 13774 views
  • Discussion

    Personal license

    Category: Custom IC Design

    By jsums

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    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 14292 views
  • Discussion

    Error in VerilogA : neither a branch nor a net name

    Category: Custom IC Design

    By sreeni

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    updated over 12 years ago by Andrew Beckett

    1 replies • 13262 views
  • Discussion

    verilog simulation

    Category: Custom IC Design

    By apple419

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    updated over 12 years ago by Andrew Beckett

    5 replies • 20136 views
  • Discussion

    Netlisting fine, but simulation fails: *Error* eval: unbound variable - currentFormSave

    Category: Custom IC Design

    By tito80

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    updated over 12 years ago by Andrew Beckett

    1 replies • 8797 views
  • Discussion

    VHDL/Verilog simulation help in Virtuoso

    Category: Custom IC Design

    By Tejaswi

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    •

    started over 12 years ago

    0 replies • 1341 views
  • Discussion

    Error invoking virtuoso IC615

    Category: Custom IC Design

    By emax

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    •

    updated over 12 years ago by theopaone

    1 replies • 13616 views
  • Discussion

    Need to place a pin on the symbol for an internal VerilogA signal

    Category: Custom IC Design

    By boast

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    •

    updated over 12 years ago by boast

    2 replies • 13934 views
  • Discussion

    CDB to OA Conversion: Layout Issue

    Category: Custom IC Design

    By sebastion

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    •

    updated over 12 years ago by Andrew Beckett

    11 replies • 19190 views
  • Discussion

    Regarding stability sims (STB) --> Over corners STB phase plots shows reversal

    Category: Custom IC Design

    By kasj

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    •

    updated over 12 years ago by kasj

    2 replies • 1526 views
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