Custom IC Design

Latest Posts

Discussion

Configure Physical Hierarchy and Virtuoso Floorplanner

Category: Custom IC Design

By corpMule

$usertype
•
updated over 14 years ago by Alex Soyer

5 replies • 17262 views
Discussion

Dynamic calculation of the power during each cycle

Category: Custom IC Design

By Ueue

$usertype
•
updated over 14 years ago by Andrew Beckett

1 replies • 13287 views
Discussion

Need to promote pins to one level Above

Category: Custom IC Design

By sathisha

$usertype
•
updated over 14 years ago by Andrew Beckett

5 replies • 18110 views
Discussion

setting for auto via to place vias despite existing cut shapes

Category: Custom IC Design

By linbo

$usertype
•
updated over 14 years ago by Andrew Beckett

3 replies • 14430 views
Discussion

Plot command failed

Category: Custom IC Design

By Renee

$usertype
•
updated over 14 years ago by Andrew Beckett

1 replies • 12943 views
Discussion

How to import cif file to virtuoso 6.1.3

Category: Custom IC Design

By wudiyyn

$usertype
•
updated over 14 years ago by StefanSL

1 replies • 13597 views
Discussion

How do I control CDLIn generating User Property information?

Category: Custom IC Design

By Amanda2

$usertype
•
updated over 14 years ago by Amanda2

6 replies • 14954 views
Discussion

IIP3 and NF measurements in cadence spectre for Fully Differential Active-RC Filter

Category: Custom IC Design

By jimito13

$usertype
•
started over 14 years ago

0 replies • 13191 views
Discussion

deselect when zoom to unconnected net?

Category: Custom IC Design

By linbo

$usertype
•
updated over 14 years ago by linbo

2 replies • 13232 views
Discussion

viewing the simulation results with viewer in cadence

Category: Custom IC Design

By Hazo

$usertype
•
updated over 14 years ago by Andrew Beckett

1 replies • 13495 views
Discussion

turning off VXL connectivity in non VXL context

Category: Custom IC Design

By linbo

$usertype
•
updated over 14 years ago by Andrew Beckett

1 replies • 13152 views
Discussion

Simulation with MATLAB generated data file as input to Anagol block

Category: Custom IC Design

By Analog Design

$usertype
•
updated over 14 years ago by Andrew Beckett

3 replies • 13922 views
Discussion

About function define

Category: Custom IC Design

By bobbygang

$usertype
•
updated over 14 years ago by bobbygang

6 replies • 15287 views
Discussion

turning off Illegal Weak-Connect check in VXL

Category: Custom IC Design

By linbo

$usertype
•
updated over 14 years ago by Quek

1 replies • 14771 views
Discussion

Abstract Generator Crash!!

Category: Custom IC Design

By eklikeroomys

$usertype
•
updated over 14 years ago by Andrew Beckett

3 replies • 13662 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.