Custom IC Design

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Discussion

Regarding cadence virtuoso installation

Category: Custom IC Design

By Simhadri

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updated over 4 years ago by Andrew Beckett

1 replies • 11547 views
Discussion

[Virtuoso layout XL] How to switch between quick align User Spacing and quick align No Spacing with single keystroke?

Category: Custom IC Design

By 94d33m

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updated over 4 years ago by Andrew Beckett

3 replies • 16831 views
Discussion

How to run encrypted Pspice model in Cadence?

Category: Custom IC Design

By Firdos

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updated over 4 years ago by Frank Wiedmann

1 replies • 11003 views
Discussion

Relative path for Ocean script in Maestro

Category: Custom IC Design

By FormerMember

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updated over 4 years ago by FormerMember

1 replies • 5185 views
Discussion

skipping digital registers in analog extracted simulations

Category: Custom IC Design

By Mohamayreh

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updated over 4 years ago by FormerMember

1 replies • 9438 views
Discussion

How to keep attached shapes of a multipart path when chopping the multipart path

Category: Custom IC Design

By Strongy2021

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started over 4 years ago

0 replies • 9219 views
Discussion

Simulation of gate leakage current using cadence

Category: Custom IC Design

By Minghao

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updated over 4 years ago by FormerMember

3 replies • 13227 views
Discussion

Frequency Measurement when clock is constant (veriloga)

Category: Custom IC Design

By ElZorro

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started over 4 years ago

0 replies • 10479 views
Discussion

Double sided spectrum in PSS simulation

Category: Custom IC Design

By Alok110

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updated over 4 years ago by Alok110

3 replies • 10881 views
Discussion

How to snap different layers to the edges of other layers? (Virtuoso Layout XL)

Category: Custom IC Design

By 94d33m

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started over 4 years ago

0 replies • 10981 views
Discussion

Generating Layout - pcellEvalFailed

Category: Custom IC Design

By nokta

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updated over 4 years ago by Andrew Beckett

6 replies • 4663 views
Discussion

EMIR simulation fails with EMIR-1099 code

Category: Custom IC Design

By ZMOS

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started over 4 years ago

0 replies • 9995 views
Discussion

Library charecterization without post-layout netlists

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by iamKarthikBK

15 replies • 14544 views
Discussion

VIVA Evaluation error for calculator expression over corners in ADE Assembler

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

2 replies • 12681 views
Discussion

Update VerilogA outputs during simulation based on values read from from

Category: Custom IC Design

By slim15

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updated over 4 years ago by Andrew Beckett

1 replies • 10077 views

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