• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
CDNS - double leaderboard script

Custom IC Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    settings for Verilog Import

    Category: Custom IC Design

    By navi2582 navi2582

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14027 views
  • Discussion

    query on spectre-MDL

    Category: Custom IC Design

    By santosh acc santosh acc

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 13273 views
  • Discussion

    mmsim72: licensing issue

    Category: Custom IC Design

    By iamlearning iamlearning

    •

    updated over 11 years ago by Andrew Beckett

    6 replies • 17319 views
  • Discussion

    Running PSS for an oscillator with a driving signal in some other part of the circuit.

    Category: Custom IC Design

    By RFStuff RFStuff

    •

    updated over 11 years ago by Andrew Beckett

    5 replies • 15302 views
  • Discussion

    How to pass parameters to a VerilogA module

    Category: Custom IC Design

    By RFStuff RFStuff

    •

    updated over 11 years ago by RFStuff

    2 replies • 16012 views
  • Discussion

    noisefile in a vdc source modeled by Verilog-A

    Category: Custom IC Design

    By Aldo2 Aldo2

    •

    updated over 11 years ago by Aldo2

    3 replies • 15494 views
  • Discussion

    spectre commandline gives : -1.11111e+36 as a result. ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression

    Category: Custom IC Design

    By samung samung

    •

    updated over 11 years ago by samung

    4 replies • 1697 views
  • Discussion

    Help me out. Error Instance(of type diode) requires the use of model...

    Category: Custom IC Design

    By Leona Leona

    •

    updated over 11 years ago by Quek

    1 replies • 2475 views
  • Discussion

    Need workaround for duplicate veriloga module name issue

    Category: Custom IC Design

    By JKupanna JKupanna

    •

    updated over 11 years ago by JKupanna

    2 replies • 15091 views
  • Discussion

    where to insert an additional transistor level circuit in digital flow?

    Category: Custom IC Design

    By Shiny Shiny

    •

    updated over 11 years ago by Quek

    1 replies • 13103 views
  • Discussion

    IO placement

    Category: Custom IC Design

    By Shameel Shameel

    •

    updated over 11 years ago by Quek

    1 replies • 13235 views
  • Discussion

    layermap file

    Category: Custom IC Design

    By bhaskarlakshmi bhaskarlakshmi

    •

    updated over 11 years ago by Quek

    1 replies • 14009 views
  • Discussion

    how to simulate delay of a wire?

    Category: Custom IC Design

    By rickyuexu rickyuexu

    •

    updated over 11 years ago by rickyuexu

    6 replies • 15931 views
  • Discussion

    analysis

    Category: Custom IC Design

    By yeong yeong

    •

    updated over 11 years ago by Andrew Beckett

    29 replies • 22489 views
  • Discussion

    Hierarchical Parasitic Extraction & Cadence Tools

    Category: Custom IC Design

    By jimito13 jimito13

    •

    updated over 11 years ago by GabrielB

    24 replies • 16860 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information