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Custom IC Design

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  • Discussion

    TIMEOUT feature

    Category: Custom IC Design

    By naga369

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    started over 4 years ago

    0 replies • 9956 views
  • Discussion

    PLL + PSS + PNOISE convergence

    Category: Custom IC Design

    By HoWei

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    •

    updated over 4 years ago by FormerMember

    17 replies • 25201 views
  • Discussion

    How to treat parasitic device as open for LVS

    Category: Custom IC Design

    By brianbranch

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10723 views
  • Discussion

    WARNING (OCN-6038) Results dc are not available loading OCEAN script

    Category: Custom IC Design

    By Victor Camacho

    $usertype

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 11882 views
  • Discussion

    Report CPU time directly in ADE Assembler

    Category: Custom IC Design

    By jehh

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    •

    updated over 4 years ago by Frank Wiedmann

    3 replies • 10075 views
  • Discussion

    Plotting phase spectrum

    Category: Custom IC Design

    By sidt

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    •

    updated over 4 years ago by sidt

    2 replies • 14001 views
  • Discussion

    Post Layout simulation accuracy

    Category: Custom IC Design

    By Fatima65

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    •

    updated over 4 years ago by Frank Wiedmann

    7 replies • 13786 views
  • Discussion

    Virtuoso Cadence crashes when opening layout viewer

    Category: Custom IC Design

    By Eric2020

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    updated over 4 years ago by Andrew Beckett

    1 replies • 10694 views
  • Discussion

    How can I enlarge the result window in the horizontal axis direction?

    Category: Custom IC Design

    By yysunj

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10197 views
  • Discussion

    Abstract Generator : ERROR (ABS-20024)

    Category: Custom IC Design

    By Chan ho

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    updated over 4 years ago by Andrew Beckett

    1 replies • 10164 views
  • Discussion

    How can I save the converged values at the nodes after the last iteration of the time step in verilog-A?

    Category: Custom IC Design

    By rhanna

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    updated over 4 years ago by rhanna

    6 replies • 11450 views
  • Discussion

    Time domain simulation of switched capacitor circuits

    Category: Custom IC Design

    By Svilen64

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10445 views
  • Discussion

    How to netlist a VHDL-AMS generic of type "time" correctly in ADE?

    Category: Custom IC Design

    By Eckhard Hennig

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    updated over 4 years ago by Andrew Beckett

    2 replies • 1956 views
  • Discussion

    save graphical waveforms into ADE-XL views just like a spectre state view

    Category: Custom IC Design

    By PBWU

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    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 12418 views
  • Discussion

    How to set a pre-run MC simulation

    Category: Custom IC Design

    By Hannahyrh

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10179 views
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