Custom IC Design

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Cadence IC 5.1 Libmanager problem

Category: Custom IC Design

By Darshak

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updated over 12 years ago by Darshak

2 replies • 13690 views
Discussion

Switch Extracted view names in ADEXL

Category: Custom IC Design

By ank0888

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updated over 12 years ago by ank0888

3 replies • 16363 views
Discussion

Error while plotting Extracted simulation results

Category: Custom IC Design

By aravindvj

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updated over 12 years ago by Andrew Beckett

7 replies • 20657 views
Discussion

ADEXL Montecarlo, only netlisting

Category: Custom IC Design

By demsar

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updated over 12 years ago by Andrew Beckett

6 replies • 16150 views
Discussion

Error in Simulating Verilog XL+Analog in spectreVerilog

Category: Custom IC Design

By ksnf3000

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updated over 12 years ago by Andrew Beckett

2 replies • 2088 views
Discussion

How to set the model parameter STIMOD in simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Alex Liao

11 replies • 20476 views
Discussion

ADE/ViVA Toggle Trace Visibility Bindkey

Category: Custom IC Design

By mconte

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updated over 12 years ago by mconte

2 replies • 1396 views
Discussion

how to list all devices and their operating region in a file

Category: Custom IC Design

By kxlux

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updated over 12 years ago by Andrew Beckett

1 replies • 14380 views
Discussion

Error in verilogA

Category: Custom IC Design

By sreeni

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updated over 12 years ago by sreeni

4 replies • 15887 views
Discussion

Cadence ADEXL: how to merge troubleshot point with rest of montecarlo data

Category: Custom IC Design

By spectrallypure

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updated over 12 years ago by Frank Wiedmann

12 replies • 19403 views
Discussion

skill to plot waveform contained in a file into w-viewer (could be VIVA)

Category: Custom IC Design

By azde

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updated over 12 years ago by Andrew Beckett

3 replies • 13910 views
Discussion

Is there a way to print model parameter using Hspice-D version2012.03 after running a simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Andrew Beckett

9 replies • 19500 views
Discussion

STB analysis stops running ... with no error in output.log

Category: Custom IC Design

By Praveen K

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updated over 12 years ago by Praveen K

2 replies • 14581 views
Discussion

Ghost of Dragged object

Category: Custom IC Design

By Anonymous

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updated over 12 years ago by Anonymous

2 replies • 13235 views
Discussion

How to search for vias with rows or columsn property in layout XL

Category: Custom IC Design

By pham777

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updated over 12 years ago by pham777

6 replies • 15069 views

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