Custom IC Design

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Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated 10 days ago by Andrew Beckett

1 replies • 221 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
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started 12 days ago

0 replies • 220 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
•
updated 12 days ago by kenc184

3 replies • 481 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty
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started 13 days ago

0 replies • 247 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421
•
updated 15 days ago by MC20250412421

6 replies • 817 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016
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started 15 days ago

0 replies • 379 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356
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started 15 days ago

0 replies • 386 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled
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started 16 days ago

0 replies • 318 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace
•
updated 17 days ago by JankoK

3 replies • 583 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424
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started 24 days ago

0 replies • 419 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048
•
updated 24 days ago by Frank Wiedmann

3 replies • 663 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424
•
started 26 days ago

0 replies • 254 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik
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updated 28 days ago by Andrew Beckett

1 replies • 463 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici
•
updated 30 days ago by Andrew Beckett

1 replies • 513 views
Discussion

Automatic routing using Cadence Virtuoso IC6.18.120

Category: Custom IC Design

By HN20250717689
•
started 1 month ago

0 replies • 429 views

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