Custom IC Design

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Inconsistent phase noise results of divide-by-2 phase using different PNOISE method

Category: Custom IC Design

By Cod Liang

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updated over 6 years ago by Frank Wiedmann

9 replies • 19766 views
Discussion

Change size of all the solder dots in the schematic

Category: Custom IC Design

By bid75

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updated over 6 years ago by bid75

6 replies • 19682 views
Discussion

A divide by zero exception has occurred

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

3 replies • 17024 views
Discussion

how to draw using y vs y?

Category: Custom IC Design

By SGGS

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updated over 6 years ago by Candido

2 replies • 21721 views
Discussion

Phase Noise simulation accuracy

Category: Custom IC Design

By Gmacera

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updated over 6 years ago by Frank Wiedmann

1 replies • 14281 views
Discussion

Cadence Liberate for characterizing

Category: Custom IC Design

By fengye

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updated over 6 years ago by fengye

8 replies • 18497 views
Discussion

LVS: Calibre Missing Instance

Category: Custom IC Design

By wgtkan

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updated over 6 years ago by wgtkan

2 replies • 19623 views
Discussion

Is there a way to customize the netlist fom subckt netlister(like ansCdlSubcktCall and ansCdlSubcktCallExtended)?

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

6 replies • 2300 views
Discussion

Exporting the waveforms from Cadence ADE to plot it in Mathlab

Category: Custom IC Design

By NorNand

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updated over 6 years ago by NorNand

2 replies • 16184 views
Discussion

It seems auCdlPutMathExprInSingleQuotes only works for subckt netlister(like ansCdlSubcktCall and ansCdlSubcktCallExtended) not for instance netlister(like ansCdlHnlPrintInst). Is it possible to make it happen too?

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

4 replies • 1534 views
Discussion

what is the difference between "parseAsCEL no" and "parseAsCEL don't use"?

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

4 replies • 2560 views
Discussion

Virtuoso 6.1.8 plotted expressions in VIVA do not fit to evaluated expressions in assembler

Category: Custom IC Design

By Michael H

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updated over 6 years ago by Michael H

2 replies • 15872 views
Discussion

Library manager shows layout cell is checked out BUT there are no lock files in the directory path.

Category: Custom IC Design

By MGoodlett

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updated over 6 years ago by Andrew Beckett

1 replies • 17998 views
Discussion

launching ModGen in Cadence virtuoso Layout editor

Category: Custom IC Design

By NorNand

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updated over 6 years ago by Andrew Beckett

1 replies • 15365 views
Discussion

Which virtuoso version is more recent, IC 6.1.7-64b or IC 6.1.7.500.17 ?

Category: Custom IC Design

By Marben

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updated over 6 years ago by Marben

6 replies • 21006 views

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