Custom IC Design

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Discussion

LayoutXL stop layers

Category: Custom IC Design

By PNadeau

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updated over 9 years ago by PNadeau

3 replies • 14710 views
Discussion

Calculator -> Using 'value' in equation

Category: Custom IC Design

By syafiq

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updated over 9 years ago by syafiq

6 replies • 18235 views
Discussion

ADEXL Direct Plot error

Category: Custom IC Design

By PNadeau

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updated over 9 years ago by PNadeau

4 replies • 14748 views
Discussion

noise summary parameters and noise simualtions

Category: Custom IC Design

By Jeni

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updated over 9 years ago by Andrew Beckett

3 replies • 16344 views
Discussion

Cadence and Windows

Category: Custom IC Design

By manudupouy

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updated over 9 years ago by manudupouy

2 replies • 18291 views
Discussion

Maximum value of measurements set on Calculator

Category: Custom IC Design

By Johanny Saenz

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updated over 9 years ago by Andrew Beckett

1 replies • 21617 views
Discussion

Add pins and pin names quickly to symbol

Category: Custom IC Design

By Tobben24

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updated over 9 years ago by SteveRFIC

4 replies • 20696 views
Discussion

Plotting the DC sweep but clipped

Category: Custom IC Design

By Pyroblast

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updated over 9 years ago by Andrew Beckett

1 replies • 14158 views
Discussion

ADEXL - Using initial conditions from a first sim in a second sim

Category: Custom IC Design

By cdonovan

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updated over 9 years ago by cdonovan

4 replies • 3826 views
Discussion

How do I save/sweep dc operating points via Jazz?

Category: Custom IC Design

By KH28

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updated over 9 years ago by Andrew Beckett

1 replies • 1041 views
Discussion

How to streamout a gds and will have an output that is flattened

Category: Custom IC Design

By jorenrefuerzo

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updated over 9 years ago by Andrew Beckett

9 replies • 21383 views
Discussion

layout XL - flag drawing touching blockage?

Category: Custom IC Design

By yeh1

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updated over 9 years ago by Andrew Beckett

1 replies • 816 views
Discussion

Using ALTER statement in ADEL/XL

Category: Custom IC Design

By AlbertoGS

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updated over 9 years ago by Andrew Beckett

6 replies • 3600 views
Discussion

Specifying verilog plusargs when recomputing hierarchy in the Virtuoso Hierarchy Editor

Category: Custom IC Design

By chiraagjuvekar

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updated over 9 years ago by Andrew Beckett

1 replies • 13517 views
Discussion

Returning multiple variables in SKILL function

Category: Custom IC Design

By RFStuff

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updated over 9 years ago by Andrew Beckett

11 replies • 19753 views

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