Custom IC Design

Latest Posts

Discussion

Cadence library and cell views

Category: Custom IC Design

By Pyroblast

$usertype
•
updated over 9 years ago by Andrew Beckett

3 replies • 17608 views
Discussion

How can I edit the purpose of Pcell'Layers

Category: Custom IC Design

By tahm

$usertype
•
updated over 9 years ago by Andrew Beckett

3 replies • 1514 views
Discussion

In WSP, how to align different layout instances tracks in top level

Category: Custom IC Design

By Ganesh 213

$usertype
•
updated over 9 years ago by Ganesh 213

2 replies • 14735 views
Discussion

QuickAlign "center" to "edge-center" deprecated in Layout 6.1.7?

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 9 years ago by Andrew Beckett

8 replies • 9827 views
Discussion

ADE-XL: How to (efficiently) sweep parameters over a "Statistical Corner"

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 9 years ago by dontpanic

2 replies • 2281 views
Discussion

IC6 constraining/placing matched transistors

Category: Custom IC Design

By stuso

$usertype
•
updated over 9 years ago by Andrew Beckett

12 replies • 6520 views
Discussion

Inconsistency between time and freq. domain results in pss plot

Category: Custom IC Design

By VLSIiitm

$usertype
•
updated over 9 years ago by VLSIiitm

1 replies • 14170 views
Discussion

ADE-XL "Saving History" very slow

Category: Custom IC Design

By Rob Gregoire

$usertype
•
updated over 9 years ago by Rob Gregoire

10 replies • 3956 views
Discussion

Using Edit-Component Display for annotating dc operating point

Category: Custom IC Design

By jdp721

$usertype
•
updated over 9 years ago by Andrew Beckett

1 replies • 13964 views
Discussion

How to trigger call-back procedure when changing cell-name of existing instance?

Category: Custom IC Design

By Sheppy

$usertype
•
updated over 9 years ago by Andrew Beckett

4 replies • 16495 views
Discussion

export def without component orientation

Category: Custom IC Design

By Polly

$usertype
•
started over 9 years ago

0 replies • 12928 views
Discussion

how to varies the threshold voltage for mos transistor??

Category: Custom IC Design

By vishnu4830

$usertype
•
updated over 9 years ago by DeeMJ

7 replies • 21964 views
Discussion

Netlist schematic to Verilog: Preserve "var real" port type across entire netlist

Category: Custom IC Design

By jyang4

$usertype
•
started over 9 years ago

0 replies • 1216 views
Discussion

Virtuoso Layout Editor net highlighting

Category: Custom IC Design

By apple419

$usertype
•
updated over 9 years ago by apple419

2 replies • 15820 views
Discussion

test vector creation for ATE

Category: Custom IC Design

By apple419

$usertype
•
updated over 9 years ago by apple419

4 replies • 16644 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.