Custom IC Design

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Discussion

What is the difference between Id and Ids notation in result browser

Category: Custom IC Design

By syafiq

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updated over 9 years ago by Andrew Beckett

1 replies • 18114 views
Discussion

pss/qpss in the same run (alter? in ADE L?)

Category: Custom IC Design

By itos

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updated over 9 years ago by Andrew Beckett

4 replies • 2579 views
Discussion

Netlisting failed with multiple Verilog-A blocks

Category: Custom IC Design

By ywyc

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updated over 9 years ago by Andrew Beckett

1 replies • 16550 views
Discussion

ams license queuing

Category: Custom IC Design

By analogcad2

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updated over 9 years ago by Sandeep4386

5 replies • 15197 views
Discussion

Generating a current waveform in Cadence

Category: Custom IC Design

By BaaB

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updated over 9 years ago by BaaB

2 replies • 14371 views
Discussion

Transient-Noise Analysis, problem with multiple run mode

Category: Custom IC Design

By Amir0098

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updated over 9 years ago by Amir0098

2 replies • 14642 views
Discussion

Problem with HSPICE Shooting Newton (SN) AC analysis in Cadence ADE

Category: Custom IC Design

By jdp721

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updated over 9 years ago by Andrew Beckett

1 replies • 14834 views
Discussion

how could i handle a dual-path PFD+CP structure when using noise aware PLL flow?

Category: Custom IC Design

By danglanggao

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updated over 9 years ago by Andrew Beckett

5 replies • 3169 views
Discussion

Using Subversion for Revision Control with Cadence

Category: Custom IC Design

By archive

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updated over 9 years ago by acook

9 replies • 21086 views
Discussion

ocnxlOutputExpr result wave - how to save to either csv or picture?

Category: Custom IC Design

By ChrHert

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started over 9 years ago

0 replies • 737 views
Discussion

Run ADE XL without netlisting each time

Category: Custom IC Design

By Nicusor

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updated over 9 years ago by rishi74

5 replies • 16865 views
Discussion

ADEXL model group

Category: Custom IC Design

By NoelCFC

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updated over 9 years ago by Andrew Beckett

1 replies • 14656 views
Discussion

input and output noise simulation with Spectre Noise analysis?

Category: Custom IC Design

By isazulkc

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updated over 9 years ago by Andrew Beckett

8 replies • 30326 views
Discussion

Monte Carlo mismatch on certain instance hierarchy level with Verilog-A model

Category: Custom IC Design

By nthoangga

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updated over 9 years ago by Andrew Beckett

1 replies • 13864 views
Discussion

Cell is not taking variable parameters

Category: Custom IC Design

By RFStuff

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updated over 9 years ago by RFStuff

2 replies • 13777 views

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