Custom IC Design

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Discussion

How to turn off blinking, diamond-shaped markers on the fet geometry in layout

Category: Custom IC Design

By SC6789

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updated over 3 years ago by SC6789

2 replies • 11424 views
Discussion

Polysilicon in 180nm TSMC

Category: Custom IC Design

By LuigiFassio

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updated over 3 years ago by SC6789

1 replies • 10660 views
Discussion

3DB bandwidth expression

Category: Custom IC Design

By sidm

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updated over 3 years ago by Andrew Beckett

3 replies • 13206 views
Discussion

Running more tests in an already finished interactive window

Category: Custom IC Design

By fastandig

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updated over 3 years ago by Andrew Beckett

6 replies • 11392 views
Discussion

Testbench for THD and IIP3 simulations

Category: Custom IC Design

By Hossein Eslahi

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updated over 3 years ago by FormerMember

5 replies • 11814 views
Discussion

Use if statement to define parameters in Monte Carlo simulation

Category: Custom IC Design

By Holz

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updated over 3 years ago by Andrew Beckett

7 replies • 12689 views
Discussion

Run Options of ADE Assembler in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

6 replies • 13855 views
Discussion

Virtuoso License Issue: status code -5.

Category: Custom IC Design

By Paulo Aguirre

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updated over 3 years ago by Andrew Beckett

1 replies • 3674 views
Discussion

Maestro - Elapsed time to results

Category: Custom IC Design

By JeyJey

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updated over 3 years ago by FormerMember

11 replies • 5663 views
Discussion

illegal weak connection warning issue

Category: Custom IC Design

By Senan

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updated over 3 years ago by Andrew Beckett

1 replies • 12849 views
Discussion

question ： standard cell symbol import to virtuoso

Category: Custom IC Design

By jackkong

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updated over 3 years ago by jackkong

10 replies • 13229 views
Discussion

$analog_node_alias() usage with vector nets

Category: Custom IC Design

By dtodorov

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updated over 3 years ago by dtodorov

1 replies • 9426 views
Discussion

Exporting device component values and operating conditions into a table in Virtuoso

Category: Custom IC Design

By sidm

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updated over 3 years ago by FormerMember

3 replies • 10373 views
Discussion

constrain the memory use in cadence

Category: Custom IC Design

By huadel

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updated over 3 years ago by SC6789

3 replies • 16416 views
Discussion

Control flow when a return from an expression is nil

Category: Custom IC Design

By delgsy

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updated over 3 years ago by FormerMember

4 replies • 11410 views

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