Custom IC Design

Latest Posts

Discussion

How to find "file signature" of design files in Cadence Virtuoso (schematics, layouts, symbols, etc.)

Category: Custom IC Design

By Cocacola

$usertype
•
updated over 3 years ago by Andrew Beckett

6 replies • 3078 views
Discussion

Transient simulation termination by VerilogA model

Category: Custom IC Design

By Senan

$usertype
•
updated over 3 years ago by Senan

4 replies • 12044 views
Discussion

Verilog Error

Category: Custom IC Design

By Lemi

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 12428 views
Discussion

Layer Generation of Multiple Layers in Virtuoso

Category: Custom IC Design

By Tom Sawyer

$usertype
•
updated over 3 years ago by Andrew Beckett

10 replies • 14227 views
Discussion

clock buffer chain jitter measurement under deterministic supply noise

Category: Custom IC Design

By YutaoLiu

$usertype
•
updated over 3 years ago by FormerMember

7 replies • 13404 views
Discussion

Determine corner-dependent setting during operating point calculation with VerilogA model

Category: Custom IC Design

By FormerMember

$usertype
•
started over 3 years ago

0 replies • 3603 views
Discussion

Monte carlo simulation question

Category: Custom IC Design

By Holz

$usertype
•
updated over 3 years ago by Holz

2 replies • 9568 views
Discussion

how to plot THD against output voltage?

Category: Custom IC Design

By sahand1400

$usertype
•
updated over 3 years ago by FormerMember

7 replies • 12930 views
Discussion

Why there is no convergence in PSS and transient if I enable "Calculate initial conditions (ic) automatically"?

Category: Custom IC Design

By Clara Dong

$usertype
•
updated over 3 years ago by FormerMember

1 replies • 4237 views
Discussion

customize the CDL netlist

Category: Custom IC Design

By MReza123

$usertype
•
started over 3 years ago

0 replies • 10240 views
Discussion

Drawing in Layout XL

Category: Custom IC Design

By progster

$usertype
•
updated over 3 years ago by Marc Heise

1 replies • 9311 views
Discussion

Can I select simulation files via design variable? And can I sweep over a set of given parameters in ADE Assembler?

Category: Custom IC Design

By SteveVrk

$usertype
•
updated over 3 years ago by SteveVrk

2 replies • 10201 views
Discussion

Output expression has evaluation errors for corner sims

Category: Custom IC Design

By BillH314

$usertype
•
updated over 3 years ago by BillH314

4 replies • 12174 views
Discussion

veriloga output

Category: Custom IC Design

By greywanderer

$usertype
•
updated over 3 years ago by greywanderer

5 replies • 11944 views
Discussion

Function to add scs file to model libraries

Category: Custom IC Design

By dragank

$usertype
•
updated over 3 years ago by Andrew Beckett

6 replies • 12676 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.