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Custom IC Design

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  • Discussion

    [ Liberate ] Cells do not have -extsim_model parameter specified in define_leafcell command

    Category: Custom IC Design

    By iamKarthikBK

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    updated over 4 years ago by iamKarthikBK

    34 replies • 23394 views
  • Discussion

    error in plotting Y vs Y

    Category: Custom IC Design

    By mmsaad66

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    updated over 4 years ago by Andrew Beckett

    3 replies • 12446 views
  • Discussion

    license to run spectre electro-thermal demo

    Category: Custom IC Design

    By jjwwlin

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    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 12890 views
  • Discussion

    Transient noise noise_fmax vs. sampling rate

    Category: Custom IC Design

    By Jere Jarvinen

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    updated over 4 years ago by Jere Jarvinen

    2 replies • 13023 views
  • Discussion

    What is the meaning of the parent purpose in a LPP?

    Category: Custom IC Design

    By RVERP

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    updated over 4 years ago by RVERP

    2 replies • 12189 views
  • Discussion

    How can I get tabular data of I-V current

    Category: Custom IC Design

    By yysunj

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11055 views
  • Discussion

    real-time tuning simulation with transient

    Category: Custom IC Design

    By threepwood06

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    updated over 4 years ago by threepwood06

    8 replies • 14819 views
  • Discussion

    SpectreMDL sensitivity analysis

    Category: Custom IC Design

    By mihaiciortuz

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    updated over 4 years ago by mihaiciortuz

    8 replies • 15792 views
  • Discussion

    Update global variables from active setup to run plan

    Category: Custom IC Design

    By rod1

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    updated over 4 years ago by rod1

    3 replies • 13529 views
  • Discussion

    Run plan for running a single test with different variables each time

    Category: Custom IC Design

    By Ernesto1

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    updated over 4 years ago by rod1

    3 replies • 13623 views
  • Discussion

    Copied adexl view have a reference to original view's history paths in data.sdb

    Category: Custom IC Design

    By PatrikOsgnach

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    updated over 4 years ago by Danielrayray

    6 replies • 4650 views
  • Discussion

    make smaller or hide overlay in Cadence Layout XL

    Category: Custom IC Design

    By hesaliveJim

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11574 views
  • Discussion

    NPORT compression "not working"

    Category: Custom IC Design

    By TommasoF

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    •

    updated over 4 years ago by TommasoF

    5 replies • 3448 views
  • Discussion

    Terminal is inherited in switch master XXX and not inherited in place master YYY

    Category: Custom IC Design

    By jjwikner

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    updated over 4 years ago by Andrew Beckett

    4 replies • 14350 views
  • Discussion

    Resistor Noise Calculation using FFT and Noise Analysis is different

    Category: Custom IC Design

    By Nader Fathy

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    updated over 4 years ago by FormerMember

    7 replies • 18250 views
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