Custom IC Design

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Discussion

How to Set Up a Config View to Easily Switch Between Schematic and Calibre of DUT for Multiple Testbenches?

Category: Custom IC Design

By Meraj Ahmad

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updated 11 months ago by Meraj Ahmad

2 replies • 4419 views
Discussion

AMS simvision cannot load big psf.trn

Category: Custom IC Design

By gkasap92

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started 11 months ago

0 replies • 2487 views
Discussion

Force virtuoso (Layout XL) to NOT create warning markers in design

Category: Custom IC Design

By CSCNalu

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updated 11 months ago by RobMan

2 replies • 3856 views
Discussion

Characterization of Full adder that use transmission gates using liberate

Category: Custom IC Design

By TM20240913386

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updated 11 months ago by TM20240913386

1 replies • 3048 views
Discussion

error when generating snp files from a variable

Category: Custom IC Design

By TommasoF

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updated 11 months ago by TommasoF

3 replies • 3222 views
Discussion

ddt VerilogA usage

Category: Custom IC Design

By AndreaD

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started 11 months ago

0 replies • 2751 views
Discussion

Display Resource Editor: Different Colors for Schematic and Layout Axis

Category: Custom IC Design

By sgcad

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updated over 1 year ago by sgcad

3 replies • 3963 views
Discussion

Quantus not running an returning error with no description

Category: Custom IC Design

By Awab

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updated over 1 year ago by ConradJ

1 replies • 4037 views
Discussion

How to get maximum value of s11 Trace

Category: Custom IC Design

By NS202408066722

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updated over 1 year ago by NS202408066722

2 replies • 2983 views
Discussion

Author and library name in sheet border

Category: Custom IC Design

By DomiHammerfall

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updated over 1 year ago by DomiHammerfall

2 replies • 3383 views
Discussion

Error using probe terminal for dspf stb analysis

Category: Custom IC Design

By unSkilled

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updated over 1 year ago by Andrew Beckett

1 replies • 3575 views
Discussion

Change code in veriloga view from external program

Category: Custom IC Design

By mikewu999

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updated over 1 year ago by Andrew Beckett

1 replies • 2848 views
Discussion

Verilog-A: Can I ignore WARNING (VACOMP-1047)

Category: Custom IC Design

By mikewu999

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updated over 1 year ago by Andrew Beckett

1 replies • 3126 views
Discussion

Transient Simulation waveform abnormal

Category: Custom IC Design

By SkkyLee

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updated over 1 year ago by hayess

1 replies • 2963 views
Discussion

Xcelium/Simvision/xrun running very slow (waiting for SimVision/Verisium Debug to connect...)

Category: Custom IC Design

By MT202407295352

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started over 1 year ago

0 replies • 1089 views

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