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Custom IC Design

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  • Discussion

    Eval error on MATLAB expressions from ADE/Maestro outputs

    Category: Custom IC Design

    By MichR MichR

    •

    updated over 1 year ago by Marc Heise

    6 replies • 2450 views
  • Discussion

    Remove update text on schematic?

    Category: Custom IC Design

    By kenc184 kenc184

    •

    updated over 1 year ago by Andrew Beckett

    4 replies • 4618 views
  • Discussion

    ADE Explorer Design Variables sweep sets

    Category: Custom IC Design

    By nfathy nfathy

    •

    updated over 1 year ago by nfathy

    3 replies • 6035 views
  • Discussion

    Post-layout simulation without spectre view in transistor cell

    Category: Custom IC Design

    By Javadgo Javadgo

    •

    updated over 1 year ago by Javadgo

    6 replies • 5656 views
  • Discussion

    ADE including a simulation file with a relative path

    Category: Custom IC Design

    By Huf Huf

    •

    started over 1 year ago

    0 replies • 3996 views
  • Discussion

    ADE (Explorer / Assembler) Stimuli Assignment as a floating voltage source

    Category: Custom IC Design

    By Huf Huf

    •

    started over 1 year ago

    0 replies • 3765 views
  • Discussion

    Can't unlock explorer run on ADE Assembler

    Category: Custom IC Design

    By Thais Thais

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 1327 views
  • Discussion

    Is it possible to setup Layout GXL to use multiple CPU cores?

    Category: Custom IC Design

    By RuihW RuihW

    •

    started over 1 year ago

    0 replies • 3844 views
  • Discussion

    VPULSE PARAMETERS INDICATION ??

    Category: Custom IC Design

    By ganesh9989 ganesh9989

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 4647 views
  • Discussion

    Change setup of the extracted netlist (Calibre view) -- extraction with QRC

    Category: Custom IC Design

    By BitanMallik BitanMallik

    •

    started over 1 year ago

    0 replies • 631 views
  • Discussion

    LEF generated with non-used layer info

    Category: Custom IC Design

    By RuihW RuihW

    •

    started over 1 year ago

    0 replies • 3917 views
  • Discussion

    Assembler Global Optimization

    Category: Custom IC Design

    By sram17 sram17

    •

    updated over 1 year ago by sram17

    1 replies • 4186 views
  • Discussion

    Device Check Asserts that only apply within a specific time window

    Category: Custom IC Design

    By dconnern33 dconnern33

    •

    started over 1 year ago

    0 replies • 4260 views
  • Discussion

    input-referred noise measurement issue

    Category: Custom IC Design

    By engmsalik321 engmsalik321

    •

    updated over 1 year ago by Andrew Beckett

    4 replies • 6650 views
  • Discussion

    ASU 7nm installation in Cadence Virtuoso

    Category: Custom IC Design

    By samanway samanway

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 4275 views
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