Custom IC Design

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Discussion

ADE L simulation problems with stimulus file

Category: Custom IC Design

By orgconfuzion

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updated over 10 years ago by Andrew Beckett

1 replies • 14724 views
Discussion

extract gate level netlist from layout

Category: Custom IC Design

By Presley

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updated over 10 years ago by Presley

2 replies • 15287 views
Discussion

split function for ic 6.1.6 - bug(?)

Category: Custom IC Design

By imaneet

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updated over 10 years ago by Quek

1 replies • 1187 views
Discussion

LSW layer color change

Category: Custom IC Design

By ash

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updated over 10 years ago by Andrew Beckett

1 replies • 17269 views
Discussion

default colors in waveform viewer

Category: Custom IC Design

By ash

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updated over 10 years ago by ash

3 replies • 18081 views
Discussion

ADEXL worst corner summary after simulations are done.

Category: Custom IC Design

By vamshiky

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updated over 10 years ago by vamshiky

4 replies • 14734 views
Discussion

automatic highlights

Category: Custom IC Design

By Karev11

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updated over 10 years ago by Andrew Beckett

1 replies • 16361 views
Discussion

finding the test that is currently selected

Category: Custom IC Design

By mlea

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updated over 10 years ago by Andrew Beckett

3 replies • 14107 views
Discussion

Assura LVS run failing

Category: Custom IC Design

By w888ku

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updated over 10 years ago by w888ku

4 replies • 19612 views
Discussion

Instance name prefix

Category: Custom IC Design

By theopaone

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updated over 10 years ago by theopaone

2 replies • 16995 views
Discussion

Tutorials analog layouts

Category: Custom IC Design

By Prakashsivam

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updated over 10 years ago by theopaone

2 replies • 16567 views
Discussion

RelXpert simulation error

Category: Custom IC Design

By rohit halba

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updated over 10 years ago by Andrew Beckett

1 replies • 15018 views
Discussion

Ultrasim: Cannot get the rectangular coordinates of resistors in Netlist-Based EM/IR Flow

Category: Custom IC Design

By Cuong Truong

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updated over 10 years ago by Cuong Truong

2 replies • 1096 views
Discussion

Can Liberate do characterization for hierarchical SPICE netlist?

Category: Custom IC Design

By dogrush

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updated over 10 years ago by Quek

1 replies • 14053 views
Discussion

not getting parasitic information inside the extracted netlist created using pvs qrc

Category: Custom IC Design

By nads

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updated over 10 years ago by Quek

1 replies • 15311 views

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