• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
CDNS - double leaderboard script

Custom IC Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    Defining Spacing Rules inside the technology file

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13524 views
  • Discussion

    How to bind spectre netlist to symbol in schematic

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    5 replies • 16884 views
  • Discussion

    how inherit parameters (w, l and mi) of schematic to layout pcell?

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    4 replies • 14157 views
  • Discussion

    analog slogan contest

    Category: Custom IC Design

    By archive archive

    •

    started over 19 years ago

    0 replies • 12736 views
  • Discussion

    analog vs digital

    Category: Custom IC Design

    By archive archive

    •

    started over 19 years ago

    0 replies • 12671 views
  • Discussion

    test from Linda

    Category: Custom IC Design

    By archive archive

    •

    started over 19 years ago

    0 replies • 12558 views
  • Discussion

    Simulating an imported VHDL

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    4 replies • 16072 views
  • Discussion

    moving / displaying instance properties

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    1 replies • 15223 views
  • Discussion

    schematic and symbol pcells?

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    2 replies • 14978 views
  • Discussion

    SpiceIn

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    2 replies • 13806 views
  • Discussion

    Figure Causing Multiple Stamped Connections

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    2 replies • 17378 views
  • Discussion

    Be sure you take the Top Care-about Surveys

    Category: Custom IC Design

    By archive archive

    •

    started over 19 years ago

    0 replies • 12523 views
  • Discussion

    Be sure to respond to the Top Care-about Surveys

    Category: Custom IC Design

    By archive archive

    •

    started over 19 years ago

    0 replies • 12539 views
  • Discussion

    VERILOGA current imbalance

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    4 replies • 14778 views
  • Discussion

    schematic parameter passing

    Category: Custom IC Design

    By archive archive

    •

    updated over 19 years ago by archive

    1 replies • 13490 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information