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Custom IC Design

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  • Discussion

    CAPTAB DETAILS

    Category: Custom IC Design

    By auto dipper

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    updated over 11 years ago by auto dipper

    12 replies • 19611 views
  • Discussion

    How to know all the layers present in a PCELL

    Category: Custom IC Design

    By RFStuff

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    updated over 11 years ago by Andrew Beckett

    3 replies • 13659 views
  • Discussion

    default settings for ViVa waveform viewer

    Category: Custom IC Design

    By vivkr

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    updated over 11 years ago by Andrew Beckett

    6 replies • 26027 views
  • Discussion

    APS:Command line: Multi-Processing

    Category: Custom IC Design

    By Ionutz

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    updated over 11 years ago by Andrew Beckett

    1 replies • 1749 views
  • Discussion

    Insufficient memory to continue{MMSIM12}.

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 689 views
  • Discussion

    SPEF file comparison for Calibre xRC and StarRC

    Category: Custom IC Design

    By frasheed

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    updated over 11 years ago by Andrew Beckett

    3 replies • 17909 views
  • Discussion

    RVE CN command equivalent to PVS

    Category: Custom IC Design

    By jorenrefuerzo

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    updated over 11 years ago by Andrew Beckett

    3 replies • 14295 views
  • Discussion

    Bind key to change Path end type(ex:extend,truncate,round,variable)

    Category: Custom IC Design

    By KarthikJaiho

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    updated over 11 years ago by KarthikJaiho

    2 replies • 1616 views
  • Discussion

    Importing .gds file in virtuoso

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 11 years ago by RFStuff

    2 replies • 15030 views
  • Discussion

    How to create layout xl for user defined pcell with same parameters as in schematic??

    Category: Custom IC Design

    By KarthikJaiho

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 13139 views
  • Discussion

    Abstract Generator : 2 layouts of a same "Memory instance" identified as "Block" and "Core" why ?

    Category: Custom IC Design

    By samung

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    updated over 11 years ago by ColinSutlieff

    1 replies • 1003 views
  • Discussion

    Netlist error when simulating BSIMCMG

    Category: Custom IC Design

    By Chen23

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    updated over 11 years ago by Chen23

    1 replies • 15823 views
  • Discussion

    ABSTRACT GENERATOR : absSelectCell for a multi-cells Library, syntax ?

    Category: Custom IC Design

    By samung

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    updated over 11 years ago by samung

    2 replies • 13376 views
  • Discussion

    Design rules for library TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block)

    Category: Custom IC Design

    By rajrevanth61

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    updated over 11 years ago by ColinSutlieff

    1 replies • 16647 views
  • Discussion

    connect all the bus lines together

    Category: Custom IC Design

    By Clidre

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    •

    updated over 11 years ago by FormerMember

    3 replies • 18639 views
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