Custom IC Design

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Discussion

" *Error* plus: can't handle (nil + nil) " during netlisting in icfb

Category: Custom IC Design

By yayla

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updated over 11 years ago by shila sh

7 replies • 14632 views
Discussion

AMS simulation taking very small step sizes. Help in finding offending connect modules?

Category: Custom IC Design

By Amblikai

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started over 11 years ago

0 replies • 13299 views
Discussion

Issue with DRC - "run is invalid"

Category: Custom IC Design

By apaj

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updated over 11 years ago by Quek

10 replies • 4539 views
Discussion

Extracting generic devices with Assura

Category: Custom IC Design

By PietroUser

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updated over 11 years ago by Andrew Beckett

3 replies • 13657 views
Discussion

Abstract Generator : abstract view with just "M1 net layer" => instead of "M1 drawing" and "M1 pin layers"

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

2 replies • 1703 views
Discussion

Assura Layout extract.rul debug

Category: Custom IC Design

By PietroUser

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updated over 11 years ago by PietroUser

2 replies • 13271 views
Discussion

Is there a function in verilogA like "break" in C or C++ ?

Category: Custom IC Design

By UUinfini

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updated over 11 years ago by Andrew Beckett

1 replies • 1540 views
Discussion

Abstract Generator : tech file and origin in LEF file

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

2 replies • 15949 views
Discussion

Pin definition in layout.oa (layer, connectivity) ?

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

2 replies • 16159 views
Discussion

Delay calculation for full adder circuit

Category: Custom IC Design

By KISHORE085

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updated over 11 years ago by KISHORE085

7 replies • 18621 views
Discussion

Virtuoso Editor Tools Menu

Category: Custom IC Design

By Octavian

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updated over 11 years ago by Octavian

2 replies • 13708 views
Discussion

Parametric analysis - voltage error in the netlist

Category: Custom IC Design

By Seokhyun Jeong

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updated over 11 years ago by Seokhyun Jeong

2 replies • 935 views
Discussion

RMS jitter from eye diagram

Category: Custom IC Design

By 34892

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updated over 11 years ago by FormerMember

8 replies • 22716 views
Discussion

Exporting Monte Carlo Simulation

Category: Custom IC Design

By parsley

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updated over 11 years ago by Andrew Beckett

8 replies • 19829 views
Discussion

Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

3 replies • 15154 views

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