Custom IC Design

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Discussion

Relative include path for a vpwlf source

Category: Custom IC Design

By TonySal

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updated over 12 years ago by Andrew Beckett

1 replies • 15043 views
Discussion

ADE XL annotation affects schematic hierarchy

Category: Custom IC Design

By Rowlf

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updated over 12 years ago by Rowlf

2 replies • 13741 views
Discussion

Personal license

Category: Custom IC Design

By jsums

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updated over 12 years ago by Andrew Beckett

1 replies • 14260 views
Discussion

Error in VerilogA : neither a branch nor a net name

Category: Custom IC Design

By sreeni

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updated over 12 years ago by Andrew Beckett

1 replies • 13234 views
Discussion

verilog simulation

Category: Custom IC Design

By apple419

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updated over 12 years ago by Andrew Beckett

5 replies • 20083 views
Discussion

Netlisting fine, but simulation fails: *Error* eval: unbound variable - currentFormSave

Category: Custom IC Design

By tito80

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updated over 12 years ago by Andrew Beckett

1 replies • 8787 views
Discussion

VHDL/Verilog simulation help in Virtuoso

Category: Custom IC Design

By Tejaswi

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started over 12 years ago

0 replies • 1338 views
Discussion

Error invoking virtuoso IC615

Category: Custom IC Design

By emax

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updated over 12 years ago by theopaone

1 replies • 13575 views
Discussion

Need to place a pin on the symbol for an internal VerilogA signal

Category: Custom IC Design

By boast

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updated over 12 years ago by boast

2 replies • 13903 views
Discussion

CDB to OA Conversion: Layout Issue

Category: Custom IC Design

By sebastion

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updated over 12 years ago by Andrew Beckett

11 replies • 19124 views
Discussion

Regarding stability sims (STB) --> Over corners STB phase plots shows reversal

Category: Custom IC Design

By kasj

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updated over 12 years ago by kasj

2 replies • 1521 views
Discussion

Generating .lib file from layout

Category: Custom IC Design

By govilv

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updated over 12 years ago by mariek

3 replies • 19702 views
Discussion

StreamOut StreamIn round-trip issue

Category: Custom IC Design

By MarceloR

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updated over 12 years ago by MarceloR

2 replies • 13614 views
Discussion

Out of memory error of Hiearchy Editor in ic5141

Category: Custom IC Design

By greatqs

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updated over 12 years ago by Andrew Beckett

1 replies • 13181 views
Discussion

ADE L: could not open logFiles during a parametric sweep on a transient simulation

Category: Custom IC Design

By apple419

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updated over 12 years ago by Andrew Beckett

3 replies • 15580 views

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