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Custom IC Design

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  • Discussion

    Timestamp.....

    Category: Custom IC Design

    By pham777 pham777

    •

    updated over 11 years ago by aflex

    2 replies • 12931 views
  • Discussion

    Reading a data file in Veriloga code

    Category: Custom IC Design

    By Sali Sali

    •

    updated over 11 years ago by Sali

    4 replies • 16817 views
  • Discussion

    help on using diode model in Spectre simulation

    Category: Custom IC Design

    By apple419 apple419

    •

    updated over 11 years ago by Andrew Beckett

    2 replies • 16880 views
  • Discussion

    saving verilog-a triggers compilation instead of just syntax check

    Category: Custom IC Design

    By danmc danmc

    •

    updated over 11 years ago by danmc

    2 replies • 13059 views
  • Discussion

    sweep variable "bs" in hb, then use VAR("bs") in output expression, not plot in ADEXL

    Category: Custom IC Design

    By Taoni Taoni

    •

    updated over 11 years ago by Andrew Beckett

    6 replies • 6876 views
  • Discussion

    Strange behavior of traponly method (MMSIM/SpectreRF)

    Category: Custom IC Design

    By norrin norrin

    •

    updated over 11 years ago by Frank Wiedmann

    2 replies • 11081 views
  • Discussion

    issue with (* cds_inherited_parameter *)

    Category: Custom IC Design

    By Fabb Fabb

    •

    updated over 11 years ago by Fabb

    4 replies • 14214 views
  • Discussion

    How to use calculator to process a set of curves in wavescan

    Category: Custom IC Design

    By bjstroll bjstroll

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 15012 views
  • Discussion

    Extraction AS/AD in Assura RCX

    Category: Custom IC Design

    By TiNat TiNat

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 644 views
  • Discussion

    ocean -nograph error

    Category: Custom IC Design

    By nigam214 nigam214

    •

    updated over 11 years ago by Andrew Beckett

    6 replies • 3396 views
  • Discussion

    During pcell evaluation in Assura LVS, is there a way to get cellview database information ?

    Category: Custom IC Design

    By windowsdee windowsdee

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 12755 views
  • Discussion

    LVS on a layout imported from Encounter versus the Physical Verilog netlist

    Category: Custom IC Design

    By Kabal Kabal

    •

    updated over 11 years ago by Andrew Beckett

    14 replies • 22929 views
  • Discussion

    Verilog-A parser and HSPICE

    Category: Custom IC Design

    By The Setlaz The Setlaz

    •

    updated over 11 years ago by The Setlaz

    7 replies • 15859 views
  • Discussion

    ADE-XL graphical outputs accessed from Skill

    Category: Custom IC Design

    By AxelS AxelS

    •

    updated over 11 years ago by AxelS

    3 replies • 13206 views
  • Discussion

    Transient simulation display time issue !

    Category: Custom IC Design

    By isazulkc isazulkc

    •

    updated over 11 years ago by isazulkc

    1 replies • 13171 views
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