Custom IC Design

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Discussion

Flattening the Multipart Path

Category: Custom IC Design

By shushan
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updated over 12 years ago by Andrew Beckett

7 replies • 17198 views
Discussion

single point AC analysis

Category: Custom IC Design

By Steve Mikes
•
updated over 12 years ago by Andrew Beckett

1 replies • 12962 views
Discussion

Post-processing non-PSF results formats through OCEAN

Category: Custom IC Design

By mnabil
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updated over 12 years ago by mnabil

4 replies • 16629 views
Discussion

finding average,dynamic, static power

Category: Custom IC Design

By PSASWALE
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started over 12 years ago

0 replies • 3163 views
Discussion

ASCII waveform file format for Virtuoso Visualization and Analysis XL?

Category: Custom IC Design

By Andy Stewart
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updated over 12 years ago by Andrew Beckett

6 replies • 18863 views
Discussion

Connectivity->Update->Layout Parameters problem

Category: Custom IC Design

By pham777
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updated over 12 years ago by pham777

9 replies • 5490 views
Discussion

OCEAN write generic procedure to plot waveforms

Category: Custom IC Design

By The Setlaz
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updated over 12 years ago by The Setlaz

6 replies • 15149 views
Discussion

Problem simulating Spice Netlist with Spectre

Category: Custom IC Design

By Oriba
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updated over 12 years ago by Andrew Beckett

7 replies • 20094 views
Discussion

Relative include path for a vpwlf source

Category: Custom IC Design

By TonySal
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updated over 12 years ago by Andrew Beckett

1 replies • 14910 views
Discussion

ADE XL annotation affects schematic hierarchy

Category: Custom IC Design

By Rowlf
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updated over 12 years ago by Rowlf

2 replies • 13618 views
Discussion

Personal license

Category: Custom IC Design

By jsums
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updated over 12 years ago by Andrew Beckett

1 replies • 14129 views
Discussion

Error in VerilogA : neither a branch nor a net name

Category: Custom IC Design

By sreeni
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updated over 12 years ago by Andrew Beckett

1 replies • 13125 views
Discussion

verilog simulation

Category: Custom IC Design

By apple419
•
updated over 12 years ago by Andrew Beckett

5 replies • 19911 views
Discussion

Netlisting fine, but simulation fails: *Error* eval: unbound variable - currentFormSave

Category: Custom IC Design

By tito80
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updated over 12 years ago by Andrew Beckett

1 replies • 8744 views
Discussion

VHDL/Verilog simulation help in Virtuoso

Category: Custom IC Design

By Tejaswi
•
started over 12 years ago

0 replies • 1312 views

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