Custom IC Design

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Discussion

VerilogA loop generate constructs not defining multiple sub modules

Category: Custom IC Design

By AAbdelRahman
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updated over 3 years ago by AAbdelRahman

8 replies • 13407 views
Discussion

How to measure node to node capacitance?

Category: Custom IC Design

By Holz
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updated over 3 years ago by FormerMember

3 replies • 12901 views
Discussion

variables from CDF parameters

Category: Custom IC Design

By amacSS
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updated over 3 years ago by Andrew Beckett

5 replies • 12401 views
Discussion

Set ignoredesigchangesduringrun locally / per session / per maestro cell

Category: Custom IC Design

By jehh
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updated over 3 years ago by Andrew Beckett

4 replies • 10315 views
Discussion

DRC Cadence

Category: Custom IC Design

By Zahir Kaka
•
updated over 3 years ago by Andrew Beckett

1 replies • 9037 views
Discussion

ERROR (ASSEMBLER-5011) and high memory usage after some long simulations

Category: Custom IC Design

By delgsy
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updated over 3 years ago by Andrew Beckett

1 replies • 9368 views
Discussion

Coplanar wavewguide with GND plane

Category: Custom IC Design

By BoniUNIPR
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updated over 3 years ago by BoniUNIPR

2 replies • 9488 views
Discussion

verilogA

Category: Custom IC Design

By abdurrahman0234
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updated over 3 years ago by Andrew Beckett

1 replies • 9216 views
Discussion

InstallScape - failed to install component: cdsPython

Category: Custom IC Design

By bernardoleite
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updated over 3 years ago by bernardoleite

5 replies • 3354 views
Discussion

Cannot select signals to be saved in ADE Explorer/Assembler; net listing is incorrect etc.

Category: Custom IC Design

By SteveVrk
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updated over 3 years ago by FormerMember

9 replies • 5755 views
Discussion

VerilogA module instance parameter override weird behavior

Category: Custom IC Design

By AAbdelRahman
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updated over 3 years ago by AAbdelRahman

7 replies • 13193 views
Discussion

Thermal noise modeling

Category: Custom IC Design

By mahdiee86
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updated over 3 years ago by Andrew Beckett

5 replies • 12528 views
Discussion

Assembler-4040 Failed to fetch results from Matlab script

Category: Custom IC Design

By Brad RFeng
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updated over 3 years ago by Andrew Beckett

1 replies • 9053 views
Discussion

Maestro file become very large

Category: Custom IC Design

By delgsy
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updated over 3 years ago by delgsy

2 replies • 9741 views
Discussion

Multipart Path Dependent Separation and Multiple Master Paths

Category: Custom IC Design

By Kevin Buck
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updated over 3 years ago by Kevin Buck

4 replies • 10452 views

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