Custom IC Design

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Discussion

Generating data in csv format from netlist simulation

Category: Custom IC Design

By sidm
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updated over 4 years ago by Andrew Beckett

3 replies • 10727 views
Discussion

2 Tone VerilogA signal source does not work in Harmonic balance

Category: Custom IC Design

By ChristophHoehn
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updated over 4 years ago by Andrew Beckett

3 replies • 10571 views
Discussion

lxSeriesTerms for a 4-port device

Category: Custom IC Design

By FormerMember
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updated over 4 years ago by Andrew Beckett

1 replies • 4193 views
Discussion

Accessing simulation variables in verilog-a without passed parameter?

Category: Custom IC Design

By MikeVP
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updated over 4 years ago by Andrew Beckett

3 replies • 12706 views
Discussion

passing a result from previous test ADEXL

Category: Custom IC Design

By stefan111
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updated over 4 years ago by stefan111

2 replies • 12748 views
Discussion

How to plot using Simulation files stored in a folder?

Category: Custom IC Design

By Shashank M Rao
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updated over 4 years ago by Andrew Beckett

2 replies • 10464 views
Discussion

Trying to make a custom bindkey for Virtuoso to work - Select by line but for certain object types only

Category: Custom IC Design

By Tom Sawyer
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updated over 4 years ago by Tom Sawyer

2 replies • 1874 views
Discussion

Multiple Noise Analysis in one Test

Category: Custom IC Design

By greywanderer
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updated over 4 years ago by greywanderer

6 replies • 13055 views
Discussion

How to use ADE assembler to annotate DC voltages

Category: Custom IC Design

By Pecman
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updated over 4 years ago by greywanderer

10 replies • 19335 views
Discussion

How can I probe the temp value in tran simulation ?

Category: Custom IC Design

By ichiro
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updated over 4 years ago by ichiro

6 replies • 15926 views
Discussion

how to plot the resistance of pseudo-resistor against the voltage node a and b ?

Category: Custom IC Design

By sahand1400
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updated over 4 years ago by FormerMember

7 replies • 15218 views
Discussion

Best way out of 2 ways to generate random voltage source (DC)?

Category: Custom IC Design

By fastandig
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updated over 4 years ago by Andrew Beckett

6 replies • 11868 views
Discussion

Please ignore

Category: Custom IC Design

By greywanderer
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updated over 4 years ago by greywanderer

2 replies • 9842 views
Discussion

Dynamic HZ node check issue

Category: Custom IC Design

By sjwprcker
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updated over 4 years ago by Andrew Beckett

1 replies • 10058 views
Discussion

Assembler outputs: change type from implicit to signal

Category: Custom IC Design

By HoWei
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updated over 4 years ago by HoWei

3 replies • 11370 views

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