Custom IC Design

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Discussion

Current density check for layout design

Category: Custom IC Design

By Senan
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updated over 4 years ago by Senan

4 replies • 13354 views
Discussion

"ERROR: attempt to access a quantity that depends on the time derivative" in Verilog-A

Category: Custom IC Design

By rhanna
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updated over 4 years ago by Andrew Beckett

13 replies • 5355 views
Discussion

Bindkeys in ADE Explorer/Assembler

Category: Custom IC Design

By crossi
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updated over 4 years ago by crossi

5 replies • 2535 views
Discussion

illegal connection CAD warning message

Category: Custom IC Design

By Senan
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started over 4 years ago

0 replies • 10803 views
Discussion

"ncelab: *E,CUVPOM " Errors... is invalid or has multiple connections

Category: Custom IC Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

1 replies • 8660 views
Discussion

Issues in using a Verilog-A output as input to a Verilog-AMS block

Category: Custom IC Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

2 replies • 12817 views
Discussion

LVS fails "nothing in layout"

Category: Custom IC Design

By nicola91it
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updated over 4 years ago by Reyvandi

4 replies • 7920 views
Discussion

issue in launching Technology file manager

Category: Custom IC Design

By skillEater
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updated over 4 years ago by Andrew Beckett

4 replies • 11096 views
Discussion

Define 2D parameter array in Verilog-A

Category: Custom IC Design

By rhanna
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updated over 4 years ago by Andrew Beckett

3 replies • 14057 views
Discussion

export and import in cadence

Category: Custom IC Design

By Farnaz
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updated over 4 years ago by Andrew Beckett

2 replies • 12064 views
Discussion

Declaration, Initialization and shifting real type arrays in VerilogAMS

Category: Custom IC Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

5 replies • 14081 views
Discussion

Thermometer code

Category: Custom IC Design

By sidm
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updated over 4 years ago by sidm

6 replies • 18122 views
Discussion

How to use version control in IC615?

Category: Custom IC Design

By dogrush
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updated over 4 years ago by KonradMa

10 replies • 20969 views
Discussion

Accessing design variables in parametric set sweeps

Category: Custom IC Design

By Naci
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updated over 4 years ago by Naci

4 replies • 12064 views
Discussion

Can't probe terminal currents from symbols in PDK

Category: Custom IC Design

By mikewu
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updated over 4 years ago by Andrew Beckett

7 replies • 3542 views

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