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Custom IC Design

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  • Discussion

    accepting 1st subckt definition when there are duplicate subckts

    Category: Custom IC Design

    By wignesb

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    updated over 4 years ago by wignesb

    4 replies • 11828 views
  • Discussion

    Two Environment Setup Issues

    Category: Custom IC Design

    By Kevin Buck

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    updated over 4 years ago by Kevin Buck

    10 replies • 14007 views
  • Discussion

    Simulation of voltage doubler

    Category: Custom IC Design

    By akmo

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    •

    updated over 4 years ago by John kaka

    2 replies • 15132 views
  • Discussion

    Overriding specifications with VAR("...") expressions

    Category: Custom IC Design

    By rod1

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    updated over 4 years ago by Andrew Beckett

    1 replies • 1221 views
  • Discussion

    Can liberate use an encrypted hspice model?

    Category: Custom IC Design

    By sherryshe

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    updated over 4 years ago by sherryshe

    9 replies • 13604 views
  • Discussion

    [SOI device]How to deal with the backgate pin (VBGP & VBGN) settings of devices with 5 terminals while running liberate?

    Category: Custom IC Design

    By sherryshe

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    started over 4 years ago

    0 replies • 1329 views
  • Discussion

    It's the same problem as the person above. Please tell me the solution

    Category: Custom IC Design

    By chanho

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 695 views
  • Discussion

    Transient simulation - adding noise after steady state

    Category: Custom IC Design

    By jehh

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    •

    updated over 4 years ago by Andrew Beckett

    5 replies • 4453 views
  • Discussion

    SnP Files extracted from PSP simulation

    Category: Custom IC Design

    By HuyDo

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    updated over 4 years ago by Andrew Beckett

    3 replies • 12585 views
  • Discussion

    SpectreRF pnoise simulation: sampled output noise of a chopping amplifer

    Category: Custom IC Design

    By SpiceMonkey

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    updated over 4 years ago by SpiceMonkey

    3 replies • 11686 views
  • Discussion

    Virtuoso Layout delete vertices

    Category: Custom IC Design

    By CSCNalu

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    updated over 4 years ago by CSCNalu

    1 replies • 10169 views
  • Discussion

    leafValue data type processing in Cadence Virtuoso

    Category: Custom IC Design

    By Senan

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    updated over 4 years ago by Senan

    7 replies • 16658 views
  • Discussion

    PVS Extraction Issue - Not finding PVS or QRC tab in Virtuoso Layout to do parasitic extraction

    Category: Custom IC Design

    By vaishakprathap

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    updated over 4 years ago by Andrew Beckett

    13 replies • 9285 views
  • Discussion

    Package Library download issue

    Category: Custom IC Design

    By Ali Shah

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10147 views
  • Discussion

    .cdsinit setting to open assembler/explorer, by default, on a new window

    Category: Custom IC Design

    By Aldo2

    $usertype

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    updated over 4 years ago by Andrew Beckett

    3 replies • 1950 views
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