Custom IC Design

Latest Posts

Discussion

Can I display connections for a node?

Category: Custom IC Design

By ichiro
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updated over 2 years ago by ichiro

10 replies • 10157 views
Discussion

invalid register number in Layout view

Category: Custom IC Design

By zinal7
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updated over 2 years ago by zinal7

2 replies • 7572 views
Discussion

Finding view name used by current ADE Explorer session

Category: Custom IC Design

By raduionescu
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updated over 2 years ago by raduionescu

2 replies • 7803 views
Discussion

Is thre a simulator function that can control the simulator's temperature in Verilog AMS?

Category: Custom IC Design

By SpiceMonkey
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updated over 2 years ago by SpiceMonkey

2 replies • 1071 views
Discussion

Why doesn't a non repeating sequence "simple" voltage source exist?

Category: Custom IC Design

By kenc184
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updated over 2 years ago by kenc184

6 replies • 3312 views
Discussion

How to show process corner information inside the plot?

Category: Custom IC Design

By delgsy
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updated over 2 years ago by delgsy

4 replies • 7766 views
Discussion

Layout XL stop layers (again)

Category: Custom IC Design

By tdtg
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updated over 2 years ago by tdtg

2 replies • 8506 views
Discussion

Availability of Sensitivity results in Assembler after corner run?

Category: Custom IC Design

By StephanWeber
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updated over 2 years ago by Andrew Beckett

1 replies • 7224 views
Discussion

How to re-use a setting for Assembler Results Table (Detailed Transposed)?

Category: Custom IC Design

By StephanWeber
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updated over 2 years ago by Andrew Beckett

1 replies • 6854 views
Discussion

unwrap family

Category: Custom IC Design

By Brad RFeng
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updated over 2 years ago by Andrew Beckett

1 replies • 7043 views
Discussion

Virtuoso command not found

Category: Custom IC Design

By VoTuanMinh
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updated over 2 years ago by Andrew Beckett

21 replies • 24588 views
Discussion

How to use corner output expression in other corners for a multiple corner sim?

Category: Custom IC Design

By vpeddireddy
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updated over 2 years ago by Andrew Beckett

4 replies • 9895 views
Discussion

Liberate: are only hidden power arcs needed when defining power arcs during STD cell characterisation?

Category: Custom IC Design

By jiacong
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started over 2 years ago

0 replies • 6921 views
Discussion

Schematic bus terminals has no corresponding layout bus terminal definition

Category: Custom IC Design

By sidm
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updated over 2 years ago by sidm

3 replies • 8111 views
Discussion

Bus termination error?

Category: Custom IC Design

By kenc184
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updated over 2 years ago by Andrew Beckett

8 replies • 10159 views

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