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Custom IC Design

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  • Discussion

    Accessing power dissipation in a Verilog module

    Category: Custom IC Design

    By vksinghal

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    updated over 5 years ago by Andrew Beckett

    1 replies • 13806 views
  • Discussion

    Missing point in AMS simulation plot when the value of the consecutive points are same

    Category: Custom IC Design

    By RFStuff

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    updated over 5 years ago by Andrew Beckett

    1 replies • 13830 views
  • Discussion

    Return a string from user-defined function in VerilogA

    Category: Custom IC Design

    By DimitarT

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    updated over 5 years ago by Andrew Beckett

    1 replies • 16418 views
  • Discussion

    Monte Carlo Ocean XL: Interrupting simulations in a script

    Category: Custom IC Design

    By Martyniuk

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    updated over 5 years ago by Andrew Beckett

    1 replies • 13955 views
  • Discussion

    technology file manager

    Category: Custom IC Design

    By skillEater

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    updated over 5 years ago by Andrew Beckett

    3 replies • 15694 views
  • Discussion

    Parameters of a FINFET

    Category: Custom IC Design

    By ElectronLearn

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    updated over 5 years ago by Andrew Beckett

    3 replies • 17797 views
  • Discussion

    extract min and max over corners for every variable step

    Category: Custom IC Design

    By skylink

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    updated over 5 years ago by skylink

    2 replies • 17121 views
  • Discussion

    How to reduce parasitics from layout

    Category: Custom IC Design

    By jyoti kandpal

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    updated over 6 years ago by FormerMember

    1 replies • 16173 views
  • Discussion

    Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis in 2019

    Category: Custom IC Design

    By Andrew Beckett

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    started over 6 years ago

    0 replies • 13285 views
  • Discussion

    layout extraction avoid a specific area

    Category: Custom IC Design

    By S Liu

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    updated over 6 years ago by Andrew Beckett

    1 replies • 13761 views
  • Discussion

    Programmatically set y-axis in VIVA in Log Scale

    Category: Custom IC Design

    By Paolo Minotti

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    updated over 6 years ago by Andrew Beckett

    6 replies • 19692 views
  • Discussion

    How to flatten a hierarchical design?

    Category: Custom IC Design

    By Fari

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    updated over 6 years ago by Andrew Beckett

    1 replies • 16049 views
  • Discussion

    trouble enabling MPT coloring in IC18

    Category: Custom IC Design

    By Stevemc12

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    updated over 6 years ago by Stevemc12

    4 replies • 15933 views
  • Discussion

    how to create own via in cadence software

    Category: Custom IC Design

    By jyoti kandpal

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    updated over 6 years ago by Andrew Beckett

    3 replies • 14092 views
  • Discussion

    newbie to skill scripting

    Category: Custom IC Design

    By cadvin

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    updated over 6 years ago by Andrew Beckett

    9 replies • 16742 views
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