Custom IC Design

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Discussion

Multiple Virtuoso/Spectre sessions sharing the same simulation folder - possible ?

Category: Custom IC Design

By HoWei

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started over 6 years ago

0 replies • 1166 views
Discussion

How to change CIW and LibraryManager font size

Category: Custom IC Design

By archers

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updated over 6 years ago by Andrew Beckett

1 replies • 27687 views
Discussion

IC616 base version above netlisting error

Category: Custom IC Design

By chqian

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updated over 6 years ago by Andrew Beckett

4 replies • 15038 views
Discussion

cds_srr() mex file exception

Category: Custom IC Design

By aravichandran

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updated over 6 years ago by Andrew Beckett

1 replies • 13842 views
Discussion

ADE XL just doesn't give me me curves!

Category: Custom IC Design

By kTC4

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updated over 6 years ago by kTC4

2 replies • 1721 views
Discussion

Plotting Vector Outputs Separately in Assembler for Monte Carlo Simulations

Category: Custom IC Design

By baltacican87

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updated over 6 years ago by baltacican87

2 replies • 14639 views
Discussion

Quantus QRC (PVS interface) error

Category: Custom IC Design

By mhkvy4

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updated over 6 years ago by mhkvy4

4 replies • 16358 views
Discussion

Copying p-cell from one library to another.

Category: Custom IC Design

By skillEater

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updated over 6 years ago by Andrew Beckett

11 replies • 18885 views
Discussion

Possible to avoid "Open Configuration or Top CellView" dialog when opening a config view?

Category: Custom IC Design

By dontpanic

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updated over 6 years ago by dontpanic

2 replies • 950 views
Discussion

SPECTRE_RF_POSTLAYOUT_EAP Environment Variable

Category: Custom IC Design

By jslaton

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updated over 6 years ago by jslaton

2 replies • 13984 views
Discussion

changing decending order in cadence schematic

Category: Custom IC Design

By SatendraMaurya

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updated over 6 years ago by Andrew Beckett

1 replies • 14141 views
Discussion

Search single vias and replace with multi vias for selected nets

Category: Custom IC Design

By FrankVater

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updated over 6 years ago by FrankVater

4 replies • 15757 views
Discussion

per-test config variables in ADE XL

Category: Custom IC Design

By jeremyh

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updated over 6 years ago by jeremyh

2 replies • 15846 views
Discussion

Verilog A: Error on altering 'paramerized' module

Category: Custom IC Design

By akak

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updated over 6 years ago by Andrew Beckett

3 replies • 1905 views
Discussion

Generating spectre netlist using si gives unexpected bus syntax

Category: Custom IC Design

By Lindi

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updated over 6 years ago by Lindi

2 replies • 15856 views

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