Custom IC Design

Latest Posts

Discussion

Update global variables from active setup to run plan

Category: Custom IC Design

By rod1

$usertype
•
updated over 4 years ago by rod1

3 replies • 12812 views
Discussion

Run plan for running a single test with different variables each time

Category: Custom IC Design

By Ernesto1

$usertype
•
updated over 4 years ago by rod1

3 replies • 12896 views
Discussion

Copied adexl view have a reference to original view's history paths in data.sdb

Category: Custom IC Design

By PatrikOsgnach

$usertype
•
updated over 4 years ago by Danielrayray

6 replies • 4280 views
Discussion

make smaller or hide overlay in Cadence Layout XL

Category: Custom IC Design

By hesaliveJim

$usertype
•
updated over 4 years ago by Andrew Beckett

1 replies • 10972 views
Discussion

NPORT compression "not working"

Category: Custom IC Design

By TommasoF

$usertype
•
updated over 4 years ago by TommasoF

5 replies • 3141 views
Discussion

Terminal is inherited in switch master XXX and not inherited in place master YYY

Category: Custom IC Design

By jjwikner

$usertype
•
updated over 4 years ago by Andrew Beckett

4 replies • 13443 views
Discussion

Resistor Noise Calculation using FFT and Noise Analysis is different

Category: Custom IC Design

By Nader Fathy

$usertype
•
updated over 4 years ago by FormerMember

7 replies • 17225 views
Discussion

Issues in accuracy of clock generation in Verilog-AMS with white noise jitter

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 4 years ago by RFStuff

10 replies • 17542 views
Discussion

How do I set transient strobeoutput to "all" in AMS simulation?

Category: Custom IC Design

By Nader Fathy

$usertype
•
updated over 4 years ago by Nader Fathy

2 replies • 1779 views
Discussion

How to plot the difference of simulation result from Monte carlo and standard simulation?

Category: Custom IC Design

By Martinsh

$usertype
•
updated over 4 years ago by Andrew Beckett

9 replies • 15107 views
Discussion

VIVA zoom horizontal/vertical

Category: Custom IC Design

By amacSS

$usertype
•
updated over 4 years ago by amacSS

2 replies • 1833 views
Discussion

Bad value "primary" for parameter - Characterising cells using Liberate

Category: Custom IC Design

By iamKarthikBK

$usertype
•
started over 4 years ago

0 replies • 1490 views
Discussion

import a Spice Model in a schematic

Category: Custom IC Design

By Friedrich

$usertype
•
updated over 4 years ago by Friedrich

3 replies • 24099 views
Discussion

Connecting PMOS body to VSS! in Layout XL

Category: Custom IC Design

By Demi

$usertype
•
updated over 4 years ago by Quek

1 replies • 20056 views
Discussion

"the following branches form a loop of rigid branches"

Category: Custom IC Design

By Jose Sarmento

$usertype
•
updated over 4 years ago by Jose Sarmento

2 replies • 3426 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.