Custom IC Design

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Discussion

Title Block strings

Category: Custom IC Design

By JEFO

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updated over 7 years ago by Andrew Beckett

5 replies • 16352 views
Discussion

RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

Category: Custom IC Design

By eklikeroomys

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updated over 7 years ago by RobB47

8 replies • 3207 views
Discussion

QRC .rcx_setup.tpl file

Category: Custom IC Design

By AlexGo

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updated over 7 years ago by AlexGo

2 replies • 14274 views
Discussion

Howto run Cadence testbench examples in ./tools/dfII/samples/artist

Category: Custom IC Design

By HoWei

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updated over 7 years ago by Andrew Beckett

1 replies • 1970 views
Discussion

Mark-net usage

Category: Custom IC Design

By Nhumai

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updated over 7 years ago by fcampana

1 replies • 15234 views
Discussion

failure with using amsd block

Category: Custom IC Design

By fatcat1206

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updated over 7 years ago by fatcat1206

6 replies • 17939 views
Discussion

usim_trim to change block parameter multiplicity (m)

Category: Custom IC Design

By KOTB

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updated over 7 years ago by Andrew Beckett

7 replies • 15318 views
Discussion

Generate SDF for custom digital layout

Category: Custom IC Design

By anmos

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updated over 7 years ago by anmos

2 replies • 15399 views
Discussion

Ideal differential mixer model in rflib

Category: Custom IC Design

By Thorin

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updated over 7 years ago by sudip

2 replies • 15730 views
Discussion

memristors

Category: Custom IC Design

By bindu madhavi

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started over 7 years ago

0 replies • 13492 views
Discussion

VIVA waveform colors/types

Category: Custom IC Design

By Steve Mikes

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updated over 7 years ago by Andrew Beckett

3 replies • 3964 views
Discussion

ADE L netlister to stop at cell name match rather than view name match

Category: Custom IC Design

By SatendraMaurya

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updated over 7 years ago by SatendraMaurya

2 replies • 13895 views
Discussion

Sweeping of variable with step as expression

Category: Custom IC Design

By Nicolas Callens

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updated over 7 years ago by Andrew Beckett

1 replies • 16406 views
Discussion

Assembler Run Plan: enforcing runs to sequence correctly

Category: Custom IC Design

By Cra1g

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updated over 7 years ago by Dimitra Papazoglou

4 replies • 16988 views
Discussion

how to reduce power in post layout simulation

Category: Custom IC Design

By jayakandpal

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started over 7 years ago

0 replies • 13693 views

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