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Custom IC Design

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  • Discussion

    Maximum metal length and single connection routing in Layout XL

    Category: Custom IC Design

    By farhan89

    •

    started over 7 years ago

    0 replies • 15165 views
  • Discussion

    Auto-select spectre model for all simulations

    Category: Custom IC Design

    By MatthewLove

    •

    updated over 7 years ago by MatthewLove

    2 replies • 15081 views
  • Discussion

    Multiple Via Cut Spacing for same ViaDefName

    Category: Custom IC Design

    By FormerMember

    •

    started over 7 years ago

    0 replies • 2436 views
  • Discussion

    Auto routing constraints in cadence virtuoso

    Category: Custom IC Design

    By farhan89

    •

    started over 7 years ago

    0 replies • 15224 views
  • Discussion

    probing signal in av_extracted_RC

    Category: Custom IC Design

    By HansB

    •

    updated over 7 years ago by Quek

    3 replies • 15236 views
  • Discussion

    Multi-Voltage domain pin checks at schematic level

    Category: Custom IC Design

    By Johanny Saenz

    •

    started over 8 years ago

    0 replies • 14808 views
  • Discussion

    Checking installation of PDK is correct

    Category: Custom IC Design

    By CxD7

    •

    updated over 8 years ago by CxD7

    2 replies • 19214 views
  • Discussion

    CDF parameters reusing default value from veriloga

    Category: Custom IC Design

    By ernie123

    •

    updated over 8 years ago by ernie123

    2 replies • 16304 views
  • Discussion

    APS: better Hyperthreading ON or OFF on the machine?

    Category: Custom IC Design

    By dontpanic

    •

    updated over 8 years ago by dontpanic

    4 replies • 17649 views
  • Discussion

    Library Manager: .cdsenv / .cdsinit settings not taking effect

    Category: Custom IC Design

    By dontpanic

    •

    updated over 8 years ago by dontpanic

    4 replies • 27881 views
  • Discussion

    design kits for a new member in cadence

    Category: Custom IC Design

    By tashtoush

    •

    updated over 8 years ago by tashtoush

    6 replies • 17939 views
  • Discussion

    fail to use VAR as 'tran' analysis parameter

    Category: Custom IC Design

    By fatcat1206

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 4855 views
  • Discussion

    How do you generate a layout from schematic in Virtuoso IC 6.1.5?

    Category: Custom IC Design

    By ernie123

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 21964 views
  • Discussion

    how to enable to show all the simulation warnings

    Category: Custom IC Design

    By enzhu

    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 16588 views
  • Discussion

    Plotting across corners with internal sweep in maestro

    Category: Custom IC Design

    By Gabriel Puech

    •

    updated over 8 years ago by Andrew Beckett

    7 replies • 20273 views
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