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Custom IC Design

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  • Discussion

    cds_get_analog_value or cgav is not correct

    Category: Custom IC Design

    By nthoangga

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 14024 views
  • Discussion

    MDL: create a new waveform and save it into a wavefile

    Category: Custom IC Design

    By PatrikOsgnach

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14046 views
  • Discussion

    Monte Carlo analysis with vprbs

    Category: Custom IC Design

    By Mirco Controller

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 13751 views
  • Discussion

    tdnoise or pnoise?

    Category: Custom IC Design

    By PeppeW90

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    •

    updated over 8 years ago by Andrew Beckett

    5 replies • 15064 views
  • Discussion

    Verilog-A model equivalent to primitive model?

    Category: Custom IC Design

    By greatqs

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    •

    updated over 8 years ago by greatqs

    3 replies • 15585 views
  • Discussion

    save expression to file in ocean-xl

    Category: Custom IC Design

    By Karev11

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 13525 views
  • Discussion

    monteCarlo results in percent instead of absolute?

    Category: Custom IC Design

    By drdanmc

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    updated over 8 years ago by Andrew Beckett

    2 replies • 13582 views
  • Discussion

    How to see the properties of two cells together which are in same layout window.

    Category: Custom IC Design

    By conrel

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    updated over 8 years ago by Andrew Beckett

    1 replies • 13607 views
  • Discussion

    Montecarlo simulation not starting in ADE-XL

    Category: Custom IC Design

    By saikatc

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    updated over 8 years ago by Andrew Beckett

    6 replies • 17060 views
  • Discussion

    stitching results of two transient simulations

    Category: Custom IC Design

    By SoniaMK

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    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 15316 views
  • Discussion

    missing instance in schematic

    Category: Custom IC Design

    By SteveRFIC

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 16052 views
  • Discussion

    Need to Set Design before issuing this command

    Category: Custom IC Design

    By bitan1990

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 13590 views
  • Discussion

    VerilogA Error running Spectre

    Category: Custom IC Design

    By kevch9988

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    •

    updated over 8 years ago by AndreyVolk

    2 replies • 13874 views
  • Discussion

    Exporting Horizontal Marker, selecting intercepts by zooming the graph doesn't work

    Category: Custom IC Design

    By Clidre

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    updated over 8 years ago by Frank Wiedmann

    1 replies • 2041 views
  • Discussion

    Parasitic extraction for interconnects

    Category: Custom IC Design

    By Fabio23

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    •

    updated over 8 years ago by drdanmc

    3 replies • 18174 views
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