Custom IC Design

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Maestro - Intersymbol Interference (ISI) Jitter measurement

Category: Custom IC Design

By firebolt3

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updated over 1 year ago by Andrew Beckett

2 replies • 964 views
Discussion

Viva XL can only display waveform of the first run of a spectremdl sweep

Category: Custom IC Design

By NightOwlPoppy

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updated over 1 year ago by NightOwlPoppy

4 replies • 4422 views
Discussion

Capacitor Shown with Red 'X' in Layout for TSMC65 pdk

Category: Custom IC Design

By SM20240729856

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updated over 1 year ago by SM20240729856

2 replies • 1281 views
Discussion

Behavioral modeling of clock gating for efficient analog simulations (Spectre)

Category: Custom IC Design

By ItsMichael

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updated over 1 year ago by Alonso Schmidt

1 replies • 3431 views
Discussion

Migration to new operating system and force compiled model recompile

Category: Custom IC Design

By JayBee

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updated over 1 year ago by TomasMelander

7 replies • 5895 views
Discussion

Move Metal offgrid back on grid

Category: Custom IC Design

By TobyK

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updated over 1 year ago by RobMan

1 replies • 3133 views
Discussion

Some error while running Quantus(Assura) Parasitc extraction run form

Category: Custom IC Design

By Sameerpy

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started over 1 year ago

0 replies • 737 views
Discussion

How can I simulate based on the random mismatch generated by a previous Monte Carlo iteration?

Category: Custom IC Design

By an wx

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updated over 1 year ago by an wx

2 replies • 3361 views
Discussion

Quantus Coupled vs Decoupled Parasitic Extraction Results

Category: Custom IC Design

By Aida

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updated over 1 year ago by Aida

2 replies • 4470 views
Discussion

Does anyone know where I can find info on the TSMC18rf (180nm) PDK?

Category: Custom IC Design

By TheCoffeeLovingStudent

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updated over 1 year ago by TheCoffeeLovingStudent

4 replies • 5852 views
Discussion

Current mirror sizing limited trans. length

Category: Custom IC Design

By JeyJey

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started over 1 year ago

0 replies • 2999 views
Discussion

Saving maestro Changes After Opening in Read-Only Mode

Category: Custom IC Design

By KTBuckON

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updated over 1 year ago by KTBuckON

2 replies • 3361 views
Discussion

Importing PSPICE .lib file into Virtuoso

Category: Custom IC Design

By IP202410071719

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updated over 1 year ago by IP202410071719

2 replies • 4828 views
Discussion

use cadence liberate to characterize a cell that has capacitance and resistance,but failed...

Category: Custom IC Design

By TH20240830782

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updated over 1 year ago by TH20240830782

2 replies • 1444 views
Discussion

regarding simulating a verilogams file in cadence for implementing mtj

Category: Custom IC Design

By JJ202409288946

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updated over 1 year ago by JJ202409288946

2 replies • 3934 views

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