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Custom IC Design

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  • Discussion

    cdl export error when lvs with dracula

    Category: Custom IC Design

    By yogeshjaiswalCAD

    •

    updated over 1 year ago by yogeshjaiswalCAD

    7 replies • 6095 views
  • Discussion

    Can't find documentation on Spectre warnings SFE-83 and SFE-47

    Category: Custom IC Design

    By mikewu999

    •

    updated over 1 year ago by Andrew Beckett

    5 replies • 2037 views
  • Discussion

    Monte Carlo Voltage Source

    Category: Custom IC Design

    By JO202503011751

    •

    updated over 1 year ago by JO202503011751

    4 replies • 6404 views
  • Discussion

    can I have a if statement for the config

    Category: Custom IC Design

    By Mooh

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 4195 views
  • Discussion

    Can't display the result of Jee

    Category: Custom IC Design

    By littleneil

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 830 views
  • Discussion

    Spectre simulation ERROR, convergence issue

    Category: Custom IC Design

    By SM202501097919

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 8208 views
  • Discussion

    HBSP simulation of Gilbert Cell Mixer

    Category: Custom IC Design

    By HuyDo

    •

    started over 1 year ago

    0 replies • 3733 views
  • Discussion

    How do I select data set for Explorer->Direct Plot ?

    Category: Custom IC Design

    By BillH314

    •

    updated over 1 year ago by BillH314

    2 replies • 1429 views
  • Discussion

    Unbound Variable 'red' in ASCII Technology File

    Category: Custom IC Design

    By JJ202502261359

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 933 views
  • Discussion

    Issue Adding New Layers to Tech ASCII File in Virtuoso 6.1.7

    Category: Custom IC Design

    By JJ202502261359

    •

    updated over 1 year ago by JJ202502261359

    2 replies • 4514 views
  • Discussion

    ERROR (VACOMP-1070): Internal Compiling Error

    Category: Custom IC Design

    By USAAWA

    •

    updated over 1 year ago by USAAWA

    2 replies • 4197 views
  • Discussion

    iPar error when used in CDF

    Category: Custom IC Design

    By JS20250120924

    •

    updated over 1 year ago by JS20250120924

    4 replies • 4896 views
  • Discussion

    Verilog AMS simulation error

    Category: Custom IC Design

    By MS202502248626

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 3981 views
  • Discussion

    Virtuoso Hierarchy Editor unable to find primitive resistor/capacitor/inductor

    Category: Custom IC Design

    By Nett

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 2250 views
  • Discussion

    transfer off maestro results history

    Category: Custom IC Design

    By VAIBHAV

    •

    started over 1 year ago

    0 replies • 3300 views
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