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Custom IC Design

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  • Discussion

    Voltage out to next stage- cadence and verilogA

    Category: Custom IC Design

    By Nishtha Sharma Nishtha Sharma

    •

    started over 9 years ago

    0 replies • 352 views
  • Discussion

    spectre error (64bit/32bit) on linux

    Category: Custom IC Design

    By Karev11 Karev11

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 4212 views
  • Discussion

    Spectre: Possible to avoid "dangling node" removal when using "deepprobe" elements?

    Category: Custom IC Design

    By dontpanic dontpanic

    •

    updated over 9 years ago by dontpanic

    2 replies • 4524 views
  • Discussion

    Simple Controlling of 20V path from 5V in cadence spectre

    Category: Custom IC Design

    By Hayderuet Hayderuet

    •

    started over 9 years ago

    0 replies • 12414 views
  • Discussion

    Importing .slib file(symbols) to Cadence library

    Category: Custom IC Design

    By Eduard Raines Eduard Raines

    •

    updated over 9 years ago by Eduard Raines

    2 replies • 2854 views
  • Discussion

    parametric analysis of mos

    Category: Custom IC Design

    By haneen haneen

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 12933 views
  • Discussion

    Spice Text for subcircuit in virtuoso

    Category: Custom IC Design

    By Lilas Lilas

    •

    updated over 9 years ago by Frank Wiedmann

    1 replies • 15860 views
  • Discussion

    Abstract Generator locking files error abs-11024

    Category: Custom IC Design

    By MoMiner1870 MoMiner1870

    •

    updated over 9 years ago by MoMiner1870

    2 replies • 13018 views
  • Discussion

    Nyquist stability test using stb analysis

    Category: Custom IC Design

    By DCashen DCashen

    •

    updated over 9 years ago by DCashen

    5 replies • 18314 views
  • Discussion

    Why doing overunder without GROW increases HPN/FPN values?

    Category: Custom IC Design

    By dummyfill dummyfill

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 1083 views
  • Discussion

    how to overwrite veriloga code in cadence

    Category: Custom IC Design

    By black tea black tea

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 13812 views
  • Discussion

    Monte Carlo simulation for device mismatch

    Category: Custom IC Design

    By sdineshkumar sdineshkumar

    •

    updated over 9 years ago by Andrew Beckett

    18 replies • 27779 views
  • Discussion

    pnoise broken?

    Category: Custom IC Design

    By itos itos

    •

    started over 9 years ago

    0 replies • 12692 views
  • Discussion

    Defining a VerilogA function in C-code referring to several shared libraries

    Category: Custom IC Design

    By Herge Herge

    •

    updated over 9 years ago by Herge

    1 replies • 13225 views
  • Discussion

    Large Scale Simulation

    Category: Custom IC Design

    By HS88 HS88

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 13144 views
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