Custom IC Design

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Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett
•
started over 14 years ago

0 replies • 27892 views
Discussion

PVS LVS not flagging device W/L mismatches in gpdk045 (IC23.1 / PVS 23.11)

Category: Custom IC Design

By RK202509013321
•
updated 1 hour ago by Andrew Beckett

2 replies • 32 views
Discussion

xrun: *F,SROOTE: Cannot find the Spectre installation

Category: Custom IC Design

By Leo 93
•
updated 15 hours ago by Andrew Beckett

3 replies • 197 views
Discussion

use DC sweep variable to set another variable

Category: Custom IC Design

By Darrell L
•
updated 17 hours ago by Darrell L

2 replies • 192 views
Discussion

automate cadence design to avoid time consuming steps for simulation using python subprocess module.

Category: Custom IC Design

By AP202507218251
•
started 1 day ago

0 replies • 54 views
Discussion

ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

Category: Custom IC Design

By yogeshjaiswalCAD
•
updated 1 day ago by Andrew Beckett

3 replies • 180 views
Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber
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updated 2 days ago by Andrew Beckett

4 replies • 493 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815
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updated 4 days ago by Andrew Beckett

1 replies • 166 views
Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya
•
updated 7 days ago by ranaya

2 replies • 262 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated 7 days ago by Andrew Beckett

1 replies • 196 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
•
started 9 days ago

0 replies • 179 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
•
updated 10 days ago by kenc184

3 replies • 453 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty
•
started 10 days ago

0 replies • 217 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421
•
updated 12 days ago by MC20250412421

6 replies • 779 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016
•
started 12 days ago

0 replies • 354 views

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