Custom IC SKILL

Latest Posts

Discussion

Recursively assign ?callback entries when creating a new pull-down menu using hiCreateMenuItem()

Category: Custom IC SKILL

By Pacher Luca
•
updated over 10 years ago by Pacher Luca

2 replies • 14178 views
Discussion

How to Edit rod Subpart connectivity using SKILL function ?

Category: Custom IC SKILL

By San
•
updated over 10 years ago by theopaone

1 replies • 13427 views
Discussion

Need help in Creating via at overlap of two metal layers

Category: Custom IC SKILL

By Bhawna1
•
updated over 10 years ago by theopaone

1 replies • 16102 views
Discussion

schematics addTitleBlock and LayoutXL : triggering question

Category: Custom IC SKILL

By samung
•
updated over 10 years ago by theopaone

1 replies • 12672 views
Discussion

[Q] Customize descend function

Category: Custom IC SKILL

By Kai1646
•
updated over 10 years ago by theopaone

1 replies • 12832 views
Discussion

Issue facing in working with concatenated list

Category: Custom IC SKILL

By varun kumar D
•
updated over 10 years ago by theopaone

1 replies • 12644 views
Discussion

How to generate a gds file from a skill file from command line.

Category: Custom IC SKILL

By ahmaddaiict
•
updated over 10 years ago by theopaone

1 replies • 14373 views
Discussion

repeated element in the list how to remove ? (issue facing in code list having the same element)

Category: Custom IC SKILL

By varun kumar D
•
updated over 10 years ago by skillUser

1 replies • 13329 views
Discussion

Add angle brackets to layout instance name

Category: Custom IC SKILL

By LongTimeNovice
•
updated over 10 years ago by LongTimeNovice

1 replies • 13328 views
Discussion

Via coloring problem

Category: Custom IC SKILL

By psill000
•
updated over 10 years ago by psill000

1 replies • 13064 views
Discussion

How to import large verilog netlist into cadence schematic?

Category: Custom IC SKILL

By mliang
•
updated over 10 years ago by anasimtiaz

5 replies • 14816 views
Discussion

Change path width with bindkey

Category: Custom IC SKILL

By jwpm
•
updated over 10 years ago by jwpm

8 replies • 16057 views
Discussion

Get cell and hierarchy wire constraint information

Category: Custom IC SKILL

By psill000
•
started over 10 years ago

0 replies • 12525 views
Discussion

[SOLVED] Verilog-(AMS) PCell with variable bus width

Category: Custom IC SKILL

By Stepahn Walter
•
updated over 10 years ago by Stepahn Walter

4 replies • 5725 views
Discussion

Text or Name used for Metal Layer using tech file

Category: Custom IC SKILL

By GyanL
•
updated over 10 years ago by GyanL

3 replies • 13788 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.