Digital Implementation

Latest Posts

Discussion

Power Stripe - Power Via Generation in Encounter

Category: Digital Implementation

By bsparkma

$usertype
•
updated over 12 years ago by Kari

1 replies • 2527 views
Discussion

CTS and Routing

Category: Digital Implementation

By amythpai

$usertype
•
updated over 12 years ago by Kari

1 replies • 14917 views
Discussion

Minstep violation and Minhole violation

Category: Digital Implementation

By amythpai

$usertype
•
updated over 12 years ago by Kari

1 replies • 14677 views
Discussion

Sliced P&R

Category: Digital Implementation

By Aram Shahinyan

$usertype
•
updated over 12 years ago by Kari

1 replies • 786 views
Discussion

net_delay calculation

Category: Digital Implementation

By archive

$usertype
•
updated over 12 years ago by Kari

1 replies • 13340 views
Discussion

dbGet query inst/term driver

Category: Digital Implementation

By fitz

$usertype
•
updated over 12 years ago by fitz

2 replies • 2867 views
Discussion

Clock Tree Synthesis Through Narrow Corridors

Category: Digital Implementation

By dfick

$usertype
•
updated over 12 years ago by fitz

2 replies • 13469 views
Discussion

Encounter Test: write a pin assigment file

Category: Digital Implementation

By oalpago

$usertype
•
updated over 12 years ago by Srikanth Y

3 replies • 16025 views
Discussion

create placement blockage for instance list

Category: Digital Implementation

By Emil M

$usertype
•
updated over 12 years ago by fitz

3 replies • 17928 views
Discussion

Negative Insertion Delay

Category: Digital Implementation

By Shuklaspeak

$usertype
•
started over 12 years ago

0 replies • 15593 views
Discussion

RTL Import to Encounter in VHDL

Category: Digital Implementation

By Kabal

$usertype
•
updated over 12 years ago by grasshopper

1 replies • 13575 views
Discussion

id problem cells with verifyGeometry

Category: Digital Implementation

By gundicad

$usertype
•
updated over 12 years ago by gundicad

2 replies • 13795 views
Discussion

multiple pins in the same net (cds_thru layout synthesis)

Category: Digital Implementation

By FrancescMoll

$usertype
•
updated over 12 years ago by fitz

1 replies • 16801 views
Discussion

Combinational loop reported by RTL compiler

Category: Digital Implementation

By chinmay123

$usertype
•
started over 12 years ago

0 replies • 15697 views
Discussion

VerifyGeometry not parsing all the sub area

Category: Digital Implementation

By AnandThibbaiah

$usertype
•
updated over 12 years ago by wally1

3 replies • 14011 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.