Digital Implementation

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Discussion

Unable to add VDD VSS pins to the verilog netlist generated by Encounter

Category: Digital Implementation

By Kent Clark

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updated over 9 years ago by Kari

1 replies • 15229 views
Discussion

ecounter read_activity_file with SAF issue

Category: Digital Implementation

By zczc99

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updated over 9 years ago by Kari

1 replies • 13976 views
Discussion

Connectivity Violation

Category: Digital Implementation

By soha

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updated over 9 years ago by Kari

1 replies • 14240 views
Discussion

Driver/Receivers Delay in Time Analysis

Category: Digital Implementation

By soha

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updated over 9 years ago by Kari

1 replies • 1049 views
Discussion

CCL map file for RC extraction in Cadence. How to convert my current one?

Category: Digital Implementation

By Clidre

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updated over 9 years ago by Kari

1 replies • 14769 views
Discussion

Disconnecting the IO Port Net

Category: Digital Implementation

By Cyansparkle

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updated over 9 years ago by Kari

2 replies • 15388 views
Discussion

Creating power PADS

Category: Digital Implementation

By MadapusiSriniv

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updated over 9 years ago by Kari

1 replies • 13834 views
Discussion

Error Saving Database caused by wires created during ECO

Category: Digital Implementation

By spalley68

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updated over 9 years ago by Kari

1 replies • 13426 views
Discussion

lots of M1 spacing errors despite having low placement density

Category: Digital Implementation

By namepalli

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updated over 9 years ago by Kari

1 replies • 13339 views
Discussion

Special open on VCC, and GND while doing connectivity check after using SRoute command

Category: Digital Implementation

By elgunidy91

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updated over 9 years ago by Kari

1 replies • 14169 views
Discussion

Enabling SI aware CTS and Optimization

Category: Digital Implementation

By anil chatrathi

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updated over 9 years ago by Kari

6 replies • 15337 views
Discussion

Usage of Buffers or buffer/inverter Combo for CCopt design

Category: Digital Implementation

By sandy2186

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updated over 9 years ago by Kari

1 replies • 3352 views
Discussion

assign statement check

Category: Digital Implementation

By tiEngr

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updated over 9 years ago by Kari

5 replies • 16696 views
Discussion

createClkTreeSpec not generating ctstch file with roots

Category: Digital Implementation

By namepalli

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updated over 9 years ago by Kari

1 replies • 13120 views
Discussion

RE: path groups encounter timing analysis

Category: Digital Implementation

By kenambo

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updated over 9 years ago by kenambo

2 replies • 15441 views

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