Digital Implementation

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Discussion

Why encounter places std cells on macro?

Category: Digital Implementation

By archive

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updated over 17 years ago by ScreenName

1 replies • 13900 views
Discussion

How to set global clock signal routing in soc encounter?

Category: Digital Implementation

By Renee

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updated over 17 years ago by Kari

1 replies • 13809 views
Discussion

senthesize sub-module

Category: Digital Implementation

By designer

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started over 17 years ago

0 replies • 13528 views
Discussion

soc encounter output to Magic

Category: Digital Implementation

By Renee

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updated over 17 years ago by Renee

4 replies • 14359 views
Discussion

First Encounter pin placement/layer

Category: Digital Implementation

By archive

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updated over 17 years ago by Kari

9 replies • 9166 views
Discussion

Number of Non Equivalence Points after comparison in LEC Conformal

Category: Digital Implementation

By Azhar

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updated over 17 years ago by Azhar

1 replies • 15699 views
Discussion

Encounter/Nanoroute - fixing DRC violations while keeping critical pre-routes untouched

Category: Digital Implementation

By ccabal

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updated over 17 years ago by ccabal

4 replies • 5960 views
Discussion

Disable clock gating check for a module.

Category: Digital Implementation

By Tongju

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started over 17 years ago

0 replies • 16530 views
Discussion

How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)"

Category: Digital Implementation

By naderi

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updated over 17 years ago by BobD

3 replies • 2966 views
Discussion

Power estimation after synthesis and Place-&-route

Category: Digital Implementation

By naderi

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started over 17 years ago

0 replies • 920 views
Discussion

about dbgGPSAutoCellFunction

Category: Digital Implementation

By archive

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updated over 17 years ago by tarekray

5 replies • 14934 views
Discussion

Encounter doesn't find pgpin in the power pad

Category: Digital Implementation

By archive

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updated over 17 years ago by admin

1 replies • 972 views
Discussion

No matching .SUBCKT statement error in LVS check

Category: Digital Implementation

By archive

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updated over 17 years ago by archive

8 replies • 22685 views
Discussion

db command to return cell PG pin layer shape

Category: Digital Implementation

By archive

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started over 17 years ago

0 replies • 13381 views
Discussion

power planning for AMS design

Category: Digital Implementation

By archive

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started over 17 years ago

0 replies • 13333 views

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