Digital Implementation

how to the error "Size of cell PADI45(80000,141660) is not an integer multiple of its site IOSite(20,400000)"

Category: Digital Implementation

LVS after place&route may fail due to clock tree buffers

Category: Digital Implementation

Using a PSpice advanced part into a subcircuit

Category: Digital Implementation

avoid use of certain cells within a subdesign

Category: Digital Implementation

how could FE extract coupled C when doing timeDesign?

Category: Digital Implementation

Regarding sample dofile for in lec verify mode

Category: Digital Implementation

How to get area results in Micron

Category: Digital Implementation

1 question on command 'congOpt'

Category: Digital Implementation

Encounter buffer footprint

Category: Digital Implementation

clockSpiceOut

Category: Digital Implementation

CDC2FAB

Category: Digital Implementation

Running a script on Package library...

Category: Digital Implementation

Adding power ring along IO

Category: Digital Implementation

All, I need good idea when making CTS of clock gating structures.

Category: Digital Implementation

setup optimisation without sdc file

Category: Digital Implementation